Specifications
DP83848C
,
DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015
www.ti.com
6.5.1.3.9 Transmitter
The encoder begins operation when the Transmit Enable input (TX_EN) goes high and converts NRZ data
to pre-emphasized Manchester data for the transceiver. For the duration of TX_EN, the serialized
Transmit Data (TXD) is encoded for the transmit-driver pair (PMD Output Pair). TXD must be valid on the
rising edge of Transmit Clock (TX_CLK). Transmission ends when TX_EN deasserts. The last transition is
always positive; it occurs at the center of the bit cell if the last bit is a one, or at the end of the bit cell if the
last bit is a zero.
6.5.1.3.10 Receiver
The decoder detects the end of a frame when no additional mid-bit transitions are detected. Within one
and a half bit times after the last bit, carrier sense is deasserted. Receive clock stays active for five more
bit times after CRS goes low, to specify the receive timings of the controller.
6.6 Memory
6.6.1 Register Block
Table 6-7. Register Map
Offset
Access Tag Description
Hex Decimal
00h 0 RW BMCR Basic Mode Control Register
01h 1 RO BMSR Basic Mode Status Register
02h 2 RO PHYIDR1 PHY Identifier Register #1
03h 3 RO PHYIDR2 PHY Identifier Register #2
04h 4 RW ANAR Auto-Negotiation Advertisement Register
05h 5 RW ANLPAR Auto-Negotiation Link Partner Ability Register (Base Page)
05h 5 RW ANLPARNP Auto-Negotiation Link Partner Ability Register (Next Page)
06h 6 RW ANER Auto-Negotiation Expansion Register
07h 7 RW ANNPTR Auto-Negotiation Next Page TX
08h-Fh 8-15 RESERVED RESERVED
Extended Registers
10h 16 RO PHYSTS PHY Status Register
11h 17 RW MICR MII Interrupt Control Register
12h 18 RW MISR MII Interrupt Status Register
13h 19 RW RESERVED RESERVED
14h 20 RO FCSCR False Carrier Sense Counter Register
15h 21 RO RECR Receive Error Counter Register
16h 22 RW PCSR PCS Sub-Layer Configuration and Status Register
17h 23 RW RBR RMII and Bypass Register
18h 24 RW LEDCR LED Direct Control Register
19h 25 RW PHYCR PHY Control Register
1Ah 26 RW 10BTSCR 10Base-T Status/Control Register
1Bh 27 RW CDCTRL1 CD Test Control Register and BIST Extensions Register
1Ch 28 RW RESERVED RESERVED
1Dh 29 RW EDCR Energy Detect Control Register
1Eh-1Fh 30-31 RW RESERVED RESERVED
48 Detailed Description Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83848C DP83848I DP83848VYB DP83848YB