Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
www.ti.com SNLS266E –MAY 2007–REVISED MARCH 2015
In order to maintain synchronization, the descrambler must continuously monitor the validity of the
unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to
constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer
starts a 722-µs countdown. Upon detection of sufficient IDLE code-groups (58 bit times) within the 722-µs
period, the hold timer will reset and begin a new countdown. This monitoring operation will continue
indefinitely given a properly operating network connection with good signal integrity. If the line state
monitor does not recognize sufficient unscrambled IDLE code-groups within the 722-µs period, the entire
descrambler will be forced out of the current state of synchronization and reset in order to re-acquire
synchronization.
6.5.1.2.8 Code-group Alignment
The code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the
descrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5
bits). Code-group alignment occurs after the J/K code-group pair is detected. Once the J/K code-group
pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary.
6.5.1.2.9 4B/5B Decoder
The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B
nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and
replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble
pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the
duration of the entire packet. This conversion ceases upon the detection of the T/R code-group pair
denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.
6.5.1.2.10 100BASE-TX Link Integrity Monitor
The 100 Base TX Link monitor ensures that a valid and stable link is established before enabling both the
Transmit and Receive PCS layer.
Signal detect must be valid for 395 µs to allow the link monitor to enter the 'Link Up' state, and enable the
transmit and receive functions.
6.5.1.2.11 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle
code-groups which is not prefixed by the code-group pair /J/K.
If this condition is detected, the DP83848VYB will assert RX_ER and present RXD[3:0] = 1110 to the MII
for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are
detected. In addition, the False Carrier Sense Counter register (FCSCR) will be incremented by one.
Once at least two IDLE code groups are detected, RX_ER and CRS become deasserted.
6.5.1.3 10BASE-T Transceiver Module
The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision,
heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not
required on the 10BASE-T interface since this is integrated inside the DP83848VYB. This section focuses
on the general 10BASE-T system level operation.
6.5.1.3.1 Operational Modes
The DP83848VYB has two basic 10BASE-T operational modes:
• Half Duplex mode
• Full Duplex mode
Copyright © 2007–2015, Texas Instruments Incorporated Detailed Description 45
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