Specifications

DP83848C

DP83848I

DP83848VYB, DP83848YB

SNLS266E –MAY 2007–REVISED MARCH 2015

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The DP83848VYB is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW)

compensation. The BLW compensation block can successfully recover the TP-PMD defined “killer”

pattern.

BLW can generally be defined as the change in the average DC content, relatively short period over time,

of an AC coupled digital transmission over a given transmission medium. (for example,, copper wire).

BLW results from the interaction between the low frequency components of a transmitted bit stream and

the frequency response of the AC coupling component(s) within the transmission system. If the low

frequency content of the digital bit stream goes below the low frequency pole of the AC coupling

transformers then the droop characteristics of the transformers will dominate resulting in potentially

serious BLW.

The digital oscilloscope plot provided in Figure 6-9 illustrates the severity of the BLW event that can

theoretically be generated during 100BASE-TX packet transmission. This event consists of approximately

800 mV of DC offset for a period of 120 ms. Left uncompensated, events such as this can cause packet

loss.

6.5.1.2.3 Signal Detect

The signal detect function of the DP83848VYB is incorporated to meet the specifications mandated by the

ANSI FDDI TP-PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage

thresholds and timing parameters.

Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3 Auto-

Negotiation by the 100BASE-TX receiver do not cause the DP83848VYB to assert signal detect.

6.5.1.2.4 MLT-3 to NRZI Decoder

The DP83848VYB decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary

NRZI data.

6.5.1.2.5 NRZI to NRZ

In a typical application, the NRZI to NRZ decoder is required in order to present NRZ formatted data to the

descrambler.

6.5.1.2.6 Serial to Parallel

The 100BASE-TX receiver includes a Serial to Parallel converter which supplies 5-bit wide data symbols

to the PCS Rx state machine.

6.5.1.2.7 Descrambler

A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an

identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the

scrambled data (SD) as represented in the equations:

SD = (UD ⊕ N) (1)

UD = (SD ⊕ N) (2)

Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the

knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the

descrambler has recognized 12 consecutive IDLE code-groups, where an unscrambled IDLE code-group

in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and

generate unscrambled data in the form of unaligned 5B code-groups.

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Product Folder Links: DP83848C DP83848I DP83848VYB DP83848YB