Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015 www.ti.com
3 Device Comparison
Table 3-1. Device Features Comparison
DEVICE TEMPERATURE RANGE TEMPERATURE GRADE
DP83848C 0°C 70°C Commercial
DP83848I -40°C 85°C Industrial
DP83848VYB -40°C 105°C Extended
DP83848YB -40°C 125°C Extreme
4 Pin Configuration and Functions
The DP83848VYB pins are classified into the following interface categories (each interface is described in
the sections that follow):
• Serial Management Interface
• MAC Data Interface
• Clock Interface
• LED Interface
• JTAG Interface
• Reset and Power Down
• Strap Options
• 10/100 Mb/s PMD Interface
• Special Connect Pins
• Power and Ground pins
NOTE
Strapping pin option. See Section 4.9 for strap definitions.
All DP83848VYB signal pins are I/O cells regardless of the particular use. The definitions below define the
functionality of the I/O cells for each pin.
Type: I Input
Type: O Output
Type: I/O Input/Output
Type: OD Open Drain
Type: PD,PU Internal Pulldown/Pullup
Type: S Strapping Pin (All strap pins have weak internal pullups or pulldowns. If the default strap
value is to be changed then an external 2.2 kΩ resistor should be used. See Section 4.9 for
details.)
4 Pin Configuration and Functions Copyright © 2007–2015, Texas Instruments Incorporated
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