Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
www.ti.com SNLS266E –MAY 2007–REVISED MARCH 2015
Table 6-3. Supported Packet Sizes at ±50ppm ±100ppm For Each Clock
Recommended Packet Size Recommended Packet Size
Start Threshold RBR[1:0] Latency Tolerance
at ±50ppm at ±100ppm
1 (4-bits) 2 bits 2,400 bytes 1,200 bytes
2 (8-bits) 6 bits 7,200 bytes 3,600 bytes
3 (12-bits) 10 bits 12,000 bytes 6,000 bytes
0 (16-bits) 14 bits 16,800 bytes 8,400 bytes
6.4.3 802.3 MII Serial Management Interface
6.4.3.1 Serial Management Register Access
The serial management MII specification defines a set of thirty-two 16-bit status and control registers that
are accessible through the management interface pins MDC and MDIO. The DP83848VYB implements all
the required MII registers as well as several optional registers. These registers are fully described in
Section 6.6.1. A description of the serial management access protocol follows.
6.4.3.2 Serial Management Access Protocol
The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data
Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is
bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown below in
Table 6-4.
Table 6-4. Typical MDIO Frame Format
MII Management Serial Protocol <idle><start><op code><device addr><reg addr><turnaround><data><idle>
Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
The MDIO pin requires a pullup resistor (1.5 kΩ) which, during IDLE and turnaround, will pull MDIO high.
In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous
logic ones on MDIO to provide the DP83848VYB with a sequence that can be used to establish
synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC
clock cycles, or by simply allowing the MDIO pullup resistor to pull the MDIO pin high during which time 32
MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to re-sync the device if
an invalid start, opcode, or turnaround bit is detected.
The DP83848VYB waits until it has received this preamble sequence before responding to any other
transaction. Once the DP83848VYB serial management port has been initialized no further preamble
sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround bit
has occurred.
The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle
line state.
Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field.
To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the
first bit of Turnaround. The addressed DP83848VYB drives the MDIO with a zero for the second bit of
turnaround and follows this with the required data. Figure 6-2 shows the timing relationship between MDC
and the MDIO as driven/received by the Station (STA) and the DP83848VYB (PHY) for a typical register
read access.
For write transactions, the station management entity writes data to the addressed DP83848VYB thus
eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity
by inserting <10>. Figure 6-3 shows the timing relationship for a typical MII register write access.
Copyright © 2007–2015, Texas Instruments Incorporated Detailed Description 35
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