Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015 www.ti.com
Figure 6-1. AN Strapping and LED Loading Example
6.3.3.2 LED Direct Control
The DP83848VYB provides another option to directly control any or all LED outputs through the LED
Direct Control Register (LEDCR), address 18h. The register does not provide read access to LEDs.
6.3.4 Internal Loopback
The DP83848VYB includes a Loopback Test mode for facilitating system diagnostics. The Loopback
mode is selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this
bit enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in
bit 3 of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be transmitted onto
the media. To ensure that the desired operating mode is maintained, Auto-Negotiation should be disabled
before selecting the Loopback mode.
6.3.5 BIST
The DP83848VYB incorporates an internal Built-in Self Test (BIST) circuit to accommodate in-circuit
testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data
paths. BIST testing can be performed with the part in the internal loopback mode or externally looped back
using a loopback cable fixture.
The BIST is implemented with independent transmit and receive paths, with the transmit block generating
a continuous stream of a pseudo random sequence. The user can select a 9 bit or 15 bit pseudo random
sequence from the PSR_15 bit in the PHY Control Register (PHYCR). The received data is compared to
the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the
BIST pass/fail status.
The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit
defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs,
the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit.
For transmit VOD testing, the Packet BIST Continuous Mode can be used to allow continuous data
transmission, setting BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh).
The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 (0x1Bh), bits
[15:8].
32 Detailed Description Copyright © 2007–2015, Texas Instruments Incorporated
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