Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015 www.ti.com
6.3 Feature Description
This section includes information on the various configuration options available with the DP83848VYB.
The configuration options described below include:
• Auto-Negotiation
• PHY Address and LEDs
• Half Duplex vs. Full Duplex
• Isolate mode
• Loopback mode
• BIST
6.3.1 Auto-Negotiation
The Auto-Negotiation function provides a mechanism for exchanging configuration information between
two ends of a link segment and automatically selecting the highest performance mode of operation
supported by both devices. Fast Link Pulse (FLP) Bursts provide the signalling used to communicate
Auto-Negotiation abilities between two devices at each end of a link segment. For further detail regarding
Auto-Negotiation, refer to Clause 28 of the IEEE 802.3 specification. The DP83848VYB supports four
different Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex, and 100
Mb/s Full Duplex), so the inclusion of Auto-Negotiation ensures that the highest performance protocol will
be selected based on the advertised ability of the Link Partner. The Auto-Negotiation function within the
DP83848VYB can be controlled either by internal register access or by the use of the AN_EN, AN1 and
AN0 pins.
6.3.1.1 Auto-Negotiation Pin Control
The state of AN_EN, AN0 and AN1 determines whether the DP83848VYB is forced into a specific mode
or Auto-Negotiation will advertise a specific ability (or set of abilities) as given in Table 6-1. These pins
allow configuration options to be selected without requiring internal register access.
The state of AN_EN, AN0 and AN1, upon power up/reset, determines the state of bits [8:5] of the ANAR
register.
The Auto-Negotiation function selected at power up or reset can be changed at any time by writing to the
Basic Mode Control Register (BMCR) at address 0x00h.
Table 6-1. Auto-Negotiation Modes
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX, Half/Full-Duplex
10BASE-T Half-Duplex
1 1 0
100BASE-TX, Half-Duplex
10BASE-T, Half/Full-Duplex
1 1 1
100BASE-TX, Half/Full-Duplex
28 Detailed Description Copyright © 2007–2015, Texas Instruments Incorporated
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