Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015 www.ti.com
AC Timing Requirements (continued)
PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT
X1 Clock to PMD Output Pair From X1 Rising edge to first bit of
T2.26.4 17 bits
Latency symbol
RMII RECEIVE TIMING
T2.27.1 X1 Clock Period 50 MHz Reference Clock 20 ns
RXD[1:0], CRS_DV, RX_DV
T2.27.2 and RX_ER output delay from 2 14 ns
X1 rising
(22)(23)(24)
From JK symbol on PMD Receive
T2.27.3 CRS ON delay (100Mb) 18.5 bits
Pair to initial assertion of CRS_DV
From TR symbol on PMD Receive
T2.27.4 CRS OFF delay (100Mb) Pair to initial deassertion of 27 bits
CRS_DV
From symbol on Receive Pair.
RXD[1:0] and RX_ER latency
T2.27.5 Elasticity buffer set to default value 38 bits
(100Mb)
(01)
ISOLATION TIMING
From software clear of bit 10 in
the BMCR register to the
T2.28.1 100 µs
transition from Isolate to Normal
mode
From Deassertion of S/W or
T2.28.2 H/W Reset to transition from 500 µs
Isolate to Normal mode
25 MHz_OUT TIMING
MII mode 20 ns
25 MHz_OUT High/Low
T2.29.1
Time
(25)
RMII mode 10 ns
25 MHz_OUT propagation
T2.29.2 Relative to X1 8 ns
delay
(25)
100 Mb/s X1 TO TX_CLK TIMING
T2.30.1 X1 to TX_CLK delay
(26)
100 Mb/s Normal mode 0 5 ns
(22) Per the RMII Specification, output delays assume a 25pF load.
(23) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may toggle
synchronously at the end of the packet to indicate CRS deassertion.
(24) RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.
(25) 25 MHz_OUT characteristics are dependent upon the X1 input characteristics.
(26) X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data.
16 Specifications Copyright © 2007–2015, Texas Instruments Incorporated
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