Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
www.ti.com SNLS266E –MAY 2007–REVISED MARCH 2015
AC Timing Requirements (continued)
PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT
10BASE-T TRANSMIT TIMING (END OF PACKET)
End of Packet High Time
T2.16.1 250 300 ns
(with '0' ending bit)
End of Packet High Time
T2.16.2 250 300 ns
(with '1' ending bit)
10BASE-T RECEIVE TIMING (START OF PACKET)
(16)
Carrier Sense Turnon Delay
T2.17.1 630 1000 ns
(PMD Input Pair to CRS)
T2.17.2 RX_DV Latency
(17)
10 bits
T2.17.3 Receive Data Latency Measurement shown from SFD 8 bits
10BASE-T RECEIVE TIMING (END OF PACKET)
T2.18.1 Carrier Sense Turn Off Delay 1 µs
10 Mb/s HEARTBEAT TIMING
T2.19.1 CD Heartbeat Delay 10 Mb/s half-duplex mode 1200 ns
T2.19.2 CD Heartbeat Duration 10 Mb/s half-duplex mode 1000 ns
10 Mb/s JABBER TIMING
T2.20.1 Jabber Activation Time 85 ms
T2.20.2 Jabber Deactivation Time 500 ms
10BASE-T NORMAL LINK PULSE TIMING
(18)
T2.21.1 Pulse Width 100 ns
T2.21.2 Pulse Period 16 ms
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING
(18)
T2.22.1 Clock, Data Pulse Width 100 ns
Clock Pulse to Clock Pulse
T2.22.2 125 µs
Period
Clock Pulse to Data Pulse
T2.22.3 Data = 1 62 µs
Period
T2.22.4 Burst Width 2 ms
T2.22.5 FLP Burst to FLP Burst Period 16 ms
100BASE-TX SIGNAL DETECT TIMING
(19)
T2.23.1 SD Internal Turnon Time 1 ms
T2.23.2 SD Internal Turnoff Time 350 µs
100 Mb/s INTERNAL LOOPBACK TIMING
T2.24.1 TX_EN to RX_DV Loopback
(20)
100 Mb/s internal loopback mode
(21)
240 ns
10 Mb/s INTERNAL LOOPBACK TIMING
T2.25.1 TX_EN to RX_DV Loopback
(20)
10 Mb/s internal loopback mode 2 µs
RMII TRANSMIT TIMING
T2.26.1 X1 Clock Period 50 MHz Reference Clock 20 ns
TXD[1:0], TX_EN, Data Setup
T2.26.2 4 ns
to X1 rising
TXD[1:0], TX_EN, Data Hold
T2.26.3 2 ns
from X1 rising
(16) 1 bit time = 100 ns in 10 Mb/s mode.
(17) 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV
(18) These specifications represent transmit timings.
(19) The signal amplitude on PMD Input Pair must be TP-PMD compliant.
(20) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
(21) Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during
which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the
initial 550µs “dead-time”.
Copyright © 2007–2015, Texas Instruments Incorporated Specifications 15
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