Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015 www.ti.com
AC Timing Requirements (continued)
PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT
100BASE-TX TRANSMIT TIMING (t
R/F
and Jitter)
100 Mb/s PMD Output Pair t
R
3 4 5 ns
and t
F
(6)
T2.8.1
100 Mb/s t
R
and t
F
500 ps
Mismatch
(7)(6)
100 Mb/s PMD Output Pair
T2.8.2 1.4 ns
Transmit Jitter
100BASE-TX RECEIVE PACKET LATENCY TIMING
(8)
T2.9.1 Carrier Sense ON Delay
(9)
100 Mb/s Normal mode
(10)
20 bits
T2.9.2 Receive Data Latency 100 Mb/s Normal mode
(10)
24 bits
100BASE-TX RECEIVE PACKET DEASSERTION TIMING
T2.10.1 Carrier Sense OFF Delay
(11)
100 Mb/s Normal mode
(10)
24 bits
10 Mb/s MII TRANSMIT TIMING
(12)
T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns
TXD[3:0], TX_EN Data Setup to
T2.11.2 10 Mb/s MII mode 25 ns
TX_CLK fall
TXD[3:0], TX_EN Data Hold
T2.11.3 10 Mb/s MII mode 0 ns
from TX_CLK rise
10 Mb/s MII RECEIVE TIMING
T2.12.1 RX_CLK High/Low Time
(13)
160 200 240 ns
RX_CLK TO RXD[3:0}, RX_DV
T2.12.2 10 Mb/s MII mode 100 ns
Delay
RX_CLK rising edge delay from
T2.12.3 10 Mb/s MII mode 100 ns
RXD[3:0], RX_DV Valid
10 Mb/s SERIAL MODE (SNI) TRANSMIT TIMING
T2.13.1 TX_CLK High Time 10 Mb/s Serial mode (SNI) 20 25 30 ns
T2.13.2 TX_CLK Low Time 10 Mb/s Serial mode (SNI) 70 75 80 ns
TXD_0, TX_EN Data Setup to
T2.13.3 10 Mb/s Serial mode (SNI) 25 ns
TX_CLK rise
TXD_0, TX_EN Data Hold from
T2.13.4 10 Mb/s Serial mode (SNI) 0 ns
TX_CLK rise
10 Mb/s SERIAL MODE (SNI) RECEIVE TIMING
T2.14.1 RX_CLK High/Low Time
(14)
35 50 65 ns
RX_CLK fall to RXD_0, RX_DV
T2.14.2 10 Mb/s Serial mode (SNI) –10 10 ns
Delay
10BASE-T TRANSMIT TIMING (START OF PACKET)
Transmit Output Delay from the
T2.15.1 10 Mb/s MII mode
(15)
3.5 bits
Falling Edge of TX_CLK
Transmit Output Delay from the
T2.15.2 10 Mb/s Serial mode (SNI)
(15)
3.5 bits
Rising Edge of TX_CLK
(6) Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude
(7) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times
(8) PMD Input Pair voltage amplitude is greater than the Signal Detect Turnon Threshold Value.
(9) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
(10) 1 bit time = 10 ns in 100 Mb/s mode.
(11) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
(12) An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on
the falling edge of TX_CLK.
(13) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low
times will not be violated.
(14) RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks. Minimum high and low
times will not be violated.
(15) 1 bit time = 100 ns in 10 Mb/s.
14 Specifications Copyright © 2007–2015, Texas Instruments Incorporated
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