Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
www.ti.com SNLS266E –MAY 2007–REVISED MARCH 2015
5.6 AC Timing Requirements
PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT
POWER-UP TIMING
MDIO is pulled high for 32-bit serial
Post Power-Up Stabilization
management initialization
T2.1.1 time prior to MDC preamble for 167 ms
X1 Clock must be stable for a min.
register accesses
(1)
of 167 ms at power up.
Hardware Configuration Pins are
described in the Section 4 section.
Hardware Configuration Latch-
T2.1.2 167 ms
in Time from power up
(1)
X1 Clock must be stable for a min.
of 167 ms at power up.
Hardware Configuration pins
T2.1.3 50 ns
transition to output drivers
RESET TIMING
Post RESET Stabilization time
MDIO is pulled high for 32-bit serial
T2.2.1 prior to MDC preamble for 3 µs
management initialization
register accesses
(2)
Hardware Configuration Latch-
Hardware Configuration Pins are
T2.2.2 in Time from the Deassertion of 3 µs
described in the Section 4 section
RESET (either soft or hard)
(2)
Hardware Configuration pins
T2.2.3 50 ns
transition to output drivers
X1 Clock must be stable for at min.
T2.2.4 RESET pulse width of 1us during RESET pulse low 1 µs
time.
MII SERIAL MANAGEMENT TIMING
MDC to MDIO (Output) Delay
T2.3.1 0 30 ns
Time
MDIO (Input) to MDC Setup
T2.3.2 10 ns
Time
MDIO (Input) to MDC Hold
T2.3.3 10 ns
Time
T2.3.4 MDC Frequency 2.5 25 MHz
100 Mb/s MII TRANSMIT TIMING
T2.4.1 TX_CLK High/Low Time 100 Mb/s Normal mode 16 20 24 ns
TXD[3:0], TX_EN Data Setup to
T2.4.2 100 Mb/s Normal mode 10 ns
TX_CLK
TXD[3:0], TX_EN Data Hold
T2.4.3 100 Mb/s Normal mode 0 ns
from TX_CLK
100 Mb/s MII RECEIVE TIMING
T2.5.1 RX_CLK High/Low Time
(3)
100 Mb/s Normal mode 16 20 24 ns
RX_CLK to RXD[3:0], RX_DV,
T2.5.2 100 Mb/s Normal mode 10 30 ns
RX_ER Delay
100BASE-TX MII TRANSMIT PACKET LATENCY TIMING
TX_CLK to PMD Output Pair
T2.6.1 100BASE-TX mode 6 bits
Latency
(4)
100BASE-TX TRANSMIT PACKET DEASSERTION TIMING
TX_CLK to PMD Output Pair
T2.7.1 100BASE-TX mode 5 bits
Deassertion
(5)
(1) In RMII Mode, the minimum Post Power-up Stabilization and Hardware Configuration Latch-in times are 84ms.
(2) It is important to choose pullup and/or pulldown resistors for each of the hardware configuration pins that provide fast RC time constants
in order to latch-in the proper value prior to the pin transitioning to an output driver.
(3) RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high
and low times will not be violated.
(4) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
(5) Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the
first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
Copyright © 2007–2015, Texas Instruments Incorporated Specifications 13
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