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DP83848C

DP83848I

DP83848VYB, DP83848YB

SNLS266E –MAY 2007–REVISED MARCH 2015

DP83848C/I/VYB/YB PHYTER™ QFP Single Port 10/100 Mb/s Ethernet

Physical Layer Transceiver

1 Introduction

1.1 Features

• Multiple Temperature Range from –40°C to 105°C • IEEE 802.3 ENDEC, 10BASE-T Transceivers and

Filters

• Low-Power 3.3-V, 0.18-µm CMOS Technology

• IEEE 802.3 PCS, 100BASE-TX Transceivers and

• Low-Power Consumption < 270 mW Typical

Filters

• 3.3-V MAC Interface

• IEEE 1149.1 JTAG

• Auto-MDIX for 10/100 Mb/s

• Integrated ANSI X3.263 Compliant TP-PMD

• Energy Detection Mode

Physical Sub-Layer with Adaptive Equalization and

• 25-MHz Clock Output

Baseline Wander Compensation

• SNI Interface (Configurable)

• Error-Free Operation up to 150 Meters

• RMII Rev. 1.2 Interface (Configurable)

• Programmable LED Support for Link, 10/100 Mb/s

• MII Serial Management Interface (MDC and MDIO)

Mode, Activity, Duplex and Collision Detect

• IEEE 802.3 MII

• Single Register Access for Complete PHY Status

• IEEE 802.3 Auto-Negotiation and Parallel

• 10/100 Mb/s Packet BIST (Built in Self Test)

Detection

1.2 Applications

• Automotive/Transportation • General Embedded Applications

• Industrial Controls and Factory Automation

1.3 Description

The number of applications requiring Ethernet connectivity continues to increase, driving Ethernet enabled

devices into harsher environments.

The DP83848C/I/VYB/YB was designed to meet the challenge of these new applications with an extended

temperature performance that goes beyond the typical Industrial temperature range. The

DP83848C/I/VYB/YB is a highly reliable, feature rich, robust device which meets IEEE 802.3 standards

over multiple temperature ranges from commercial to extreme temperatures. This device is ideally suited

for harsh environments such as wireless remote base stations, automotive/transportation, and industrial

control applications.

It offers enhanced ESD protection and the choice of an MII or RMII interface for maximum flexibility in

MPU selection; all in a 48 pin package.

The DP83848VYB extends the leadership position of the PHYTER™ family of devices with a wide

operating temperature range. The TI line of PHYTER transceivers builds on decades of Ethernet expertise

to offer the high performance and flexibility that allows the end user an easy implementation tailored to

meet these application needs.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

DP83848VYB/YB HLQFP (48)

7.00 mm × 7.00 mm

DP83848I/C LQFP (48)

(1) For more information, see Section 9, Mechanical, Packaging, and Orderable Information.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Summary of content (82 pages)

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Product Folder Sample & Buy Tools & Software Technical Documents Support & Community DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 DP83848C/I/VYB/YB PHYTER™ QFP Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver 1 Introduction 1.1 Features 1 • • • • • • • • • • • • Multiple Temperature Range from –40°C to 105°C Low-Power 3.3-V, 0.18-µm CMOS Technology Low-Power Consumption < 270 mW Typical 3.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 1.4 Functional Block Diagram 2 Introduction www.ti.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Table of Contents 1 2 3 4 5 Introduction ............................................... 1 5.3 Recommended Operating Conditions ............... 11 1.1 Features .............................................. 1 5.4 Thermal Information ................................. 11 1.2 Applications ........................................... 1 5.5 DC Specifications ................................... 12 1.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com 3 Device Comparison Table 3-1.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com 4.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 4.2 www.ti.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SIGNAL NAME SNLS266E – MAY 2007 – REVISED MARCH 2015 TYPE PIN # DESCRIPTION I S, I, PD 3 4 5 6 MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode). RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50 MHz reference clock.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 4.6 www.ti.com LED Interface See Table 6-2 for LED Mode Selection. SIGNAL NAME TYPE PIN # DESCRIPTION LED_LINK S, O, PU 28 LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good. LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SIGNAL NAME SNLS266E – MAY 2007 – REVISED MARCH 2015 TYPE PIN # PHYAD0 (COL) PHYAD1 (RXD1_0) PHYAD2 (RXD0_1) PHYAD3 (RXD1_2) PHYAD4 (RXD1_3) S, O, PU S, O, PD 42 43 44 45 46 PHY ADDRESS [4:0]: The DP83848VYB provides five PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset. The DP83848VYB supports PHY Address strapping values 0 (<00000>) through 31 (<11111>).
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 SIGNAL NAME RD-, RD+ www.ti.com TYPE PIN # I/O 13 14 DESCRIPTION Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100BASE-TX or 10BASE-T signaling. In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair. These pins require 3.3-V bias for operation. 4.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 5 Specifications 5.1 Absolute Maximum Ratings (1) (2) MIN MAX UNIT Supply Voltage (VCC) –0.5 4.2 V DC Input Voltage (VIN) –0.5 VCC + 0.5 V DC Output Voltage (VOUT) –0.5 VCC + 0.5 V 121.5 °C 260 °C 150 °C Maximum Die Temperature Lead Temperature (TL) (Soldering, 10 sec.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 5.5 www.ti.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com 5.6 SNLS266E – MAY 2007 – REVISED MARCH 2015 AC Timing Requirements PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT POWER-UP TIMING T2.1.1 Post Power-Up Stabilization time prior to MDC preamble for register accesses (1) T2.1.2 Hardware Configuration Latchin Time from power up (1) T2.1.3 Hardware Configuration pins transition to output drivers MDIO is pulled high for 32-bit serial management initialization X1 Clock must be stable for a min.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com AC Timing Requirements (continued) PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT 3 4 5 ns 100 Mb/s tR and tF Mismatch (7) (6) 500 ps 100 Mb/s PMD Output Pair Transmit Jitter 1.4 ns 100BASE-TX TRANSMIT TIMING (tR/F and Jitter) 100 Mb/s PMD Output Pair tR and tF (6) T2.8.1 T2.8.2 100BASE-TX RECEIVE PACKET LATENCY TIMING (8) T2.9.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 AC Timing Requirements (continued) PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT 250 300 ns 250 300 ns 10BASE-T TRANSMIT TIMING (END OF PACKET) T2.16.1 T2.16.2 End of Packet High Time (with '0' ending bit) End of Packet High Time (with '1' ending bit) 10BASE-T RECEIVE TIMING (START OF PACKET) (16) T2.17.1 Carrier Sense Turnon Delay (PMD Input Pair to CRS) T2.17.2 RX_DV Latency (17) T2.17.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com AC Timing Requirements (continued) PARAMETER T2.26.4 DESCRIPTION X1 Clock to PMD Output Pair Latency NOTES MIN TYP MAX UNIT From X1 Rising edge to first bit of symbol 17 bits 50 MHz Reference Clock 20 ns RMII RECEIVE TIMING T2.27.1 X1 Clock Period T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising (22) (23) (24) T2.27.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Figure 5-1. Power-Up Timing Figure 5-2.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Figure 5-3. MII Serial Management Timing Figure 5-4. 100 Mb/s MII Transmit Timing Figure 5-5. 100 Mb/s MII Receive Timing Figure 5-6.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Figure 5-7. 100BASE-TX Transmit Packet Deassertion Timing Figure 5-8. 100BASE-TX Transmit Timing (tR/F and Jitter) Figure 5-9.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Figure 5-10. 100BASE-TX Receive Packet Deassertion Timing Figure 5-11. 10 Mb/s MII Transmit Timing Figure 5-12. 10 Mb/s MII Receive Timing Figure 5-13. 10 Mb/s Serial Mode (SNI) Transmit Timing Figure 5-14.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 TX_CLK TX_EN TXD T2.15.2 PMD Output Pair T2.15.1 Figure 5-15. 10BASE-T Transmit Timing (Start of Packet) Figure 5-16. 10BASE-T Transmit Timing (End of Packet) 1st SFD Bit Decoded 1 0 1 0 1 0 1 0 1 0 1 1 TPRDr T2.17.1 CRS RX_CLK T2.17.2 RX_DV T2.17.3 RXD[3:0] 0000 Preamble SFD Data Figure 5-17. 10BASE-T Receive Timing (Start of Packet) Figure 5-18.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Figure 5-19. 10 Mb/s Heartbeat Timing Figure 5-20. 10 Mb/s Jabber Timing Figure 5-21. 10BASE-T Normal Link Pulse Timing Figure 5-22. Auto-Negotiation Fast Link Pulse (FLP) Timing Figure 5-23.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Figure 5-24. 100 Mb/s Internal Loopback Timing Figure 5-25.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Figure 5-26. RMII Transmit Timing Figure 5-27. RMII Receive Timing Figure 5-28. Isolation Timing Figure 5-29.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Figure 5-30.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com 6 Detailed Description 6.1 Overview The device is 10/100 Mbps Ethernet transceiver with an extended temperature range of -40°C to 105°C. The ability to perform over extreme temperatures makes this device ideal for demanding environments like Automotive, Transportation and Industrial Applications. The device is AEC-Q100 Grade 2 certified. Its 3.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com 6.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 6.3 www.ti.com Feature Description This section includes information on the various configuration options available with the DP83848VYB. The configuration options described below include: • Auto-Negotiation • PHY Address and LEDs • Half Duplex vs. Full Duplex • Isolate mode • Loopback mode • BIST 6.3.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com 6.3.1.2 SNLS266E – MAY 2007 – REVISED MARCH 2015 Auto-Negotiation Register Control When Auto-Negotiation is enabled, the DP83848VYB transmits the abilities programmed into the AutoNegotiation Advertisement register (ANAR) at address 04h through FLP Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and Full Duplex modes may be selected. Auto-Negotiation Priority Resolution: 1. 100BASE-TX Full Duplex (Highest Priority) 2.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com If the DP83848VYB completes Auto-Negotiation as a result of Parallel Detection, bits 5 and 7 within the ANLPAR register will be set to reflect the mode of operation present in the Link Partner. Note that bits 4:0 of the ANLPAR will also be set to 00001 based on a successful parallel detection to indicate a valid 802.3 selector field.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Table 6-2.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Figure 6-1. AN Strapping and LED Loading Example 6.3.3.2 LED Direct Control The DP83848VYB provides another option to directly control any or all LED outputs through the LED Direct Control Register (LEDCR), address 18h. The register does not provide read access to LEDs. 6.3.4 Internal Loopback The DP83848VYB includes a Loopback Test mode for facilitating system diagnostics.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com 6.3.6 SNLS266E – MAY 2007 – REVISED MARCH 2015 Energy Detect Mode When Energy Detect is enabled and there is no activity on the cable, the DP83848C/I/VYB/YB will remain in a low power mode while monitoring the transmission line. Activity on the line will cause the device to go through a normal power-up sequence.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com If a collision occurs during a receive operation, it is immediately reported by the COL signal. When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1 µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. 6.4.1.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Table 6-3. Supported Packet Sizes at ±50ppm ±100ppm For Each Clock Start Threshold RBR[1:0] Latency Tolerance Recommended Packet Size at ±50ppm Recommended Packet Size at ±100ppm 1 (4-bits) 2 bits 2,400 bytes 1,200 bytes 2 (8-bits) 6 bits 7,200 bytes 3,600 bytes 3 (12-bits) 10 bits 12,000 bytes 6,000 bytes 0 (16-bits) 14 bits 16,800 bytes 8,400 bytes 6.4.3 802.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Figure 6-2. Typical MDC/MDIO Read Operation Figure 6-3. Typical MDC/MDIO Write Operation 6.4.3.3 Serial Management Preamble Suppression The DP83848VYB supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode Status Register (BMSR, address 01h.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Table 6-5. PHY Address Mapping Pin # PHYAD Function 42 PHYAD0 RXD Function COL 43 PHYAD1 RXD_0 44 PHYAD2 RXD_1 45 PHYAD3 RXD_2 46 PHYAD4 RXD_3 The DP83848VYB can be set to respond to any of 32 possible PHY addresses through strap pins. The information is latched into the PHYCR register (address 19h, bits [4:0]) at device power up and hardware reset.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 6.4.6 www.ti.com Half Duplex vs. Full Duplex The DP83848VYB supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds. Half-duplex relies on the CSMA/CD protocol to handle collisions and network access. In Half-Duplex mode, CRS responds to both transmit and receive activity in order to maintain compliance with the IEEE 802.3 specification.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com 6.5 SNLS266E – MAY 2007 – REVISED MARCH 2015 Programming 6.5.1 Architecture This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in the following: • 100BASE-TX Transmitter • 100BASE-TX Receiver • 10BASE-T Transceiver Module 6.5.1.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Table 6-6.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com 6.5.1.1.2 SNLS266E – MAY 2007 – REVISED MARCH 2015 Scrambler The scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com 6.5.1.2.1 Analog Front End In addition to the Digital Equalization and Gain Control, the DP83848VYB includes Analog Equalization and Gain Control in the Analog Front End. The Analog Equalization reduces the amount of Digital Equalization required in the DSP. 6.5.1.2.2 Digital Signal Processor The Digital Signal Processor includes Adaptive Equalization with Gain Control and Base Line Wander Compensation.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation, requires significant compensation which will overcompensate for shorter, less attenuating lengths.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com The DP83848VYB is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TP-PMD defined “killer” pattern. BLW can generally be defined as the change in the average DC content, relatively short period over time, of an AC coupled digital transmission over a given transmission medium. (for example,, copper wire).
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 In order to maintain synchronization, the descrambler must continuously monitor the validity of the unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer starts a 722-µs countdown.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com 6.5.1.3.1.1 Half Duplex Mode In Half Duplex mode the DP83848VYB functions as a standard IEEE 802.3 10BASE-T transceiver supporting the CSMA/CD protocol. 6.5.1.3.1.2 Full Duplex Mode In Full Duplex mode the DP83848VYB is capable of simultaneously transmitting and receiving without asserting the collision signal. The DP83848VYB's 10 Mb/s ENDEC is designed to encode and decode simultaneously. 6.5.1.3.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 When heartbeat is enabled, approximately 1 µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10-bit times is generated to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. The SQE test is inhibited when the PHY is set in full duplex mode. SQE can also be inhibited by setting the HEARTBEAT_DIS bit in the 10BTSCR register. 6.5.1.3.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com 6.5.1.3.9 Transmitter The encoder begins operation when the Transmit Enable input (TX_EN) goes high and converts NRZ data to pre-emphasized Manchester data for the transceiver. For the duration of TX_EN, the serialized Transmit Data (TXD) is encoded for the transmit-driver pair (PMD Output Pair). TXD must be valid on the rising edge of Transmit Clock (TX_CLK). Transmission ends when TX_EN deasserts.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Table 6-8.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Table 6-8.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com 6.6.1.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Table 6-9. Basic Mode Control Register (BMCR), address 0x00h (continued) Bit Bit Name Default 8 DUPLEX MODE Strap, RW Description Duplex Mode: When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected. 1 = Full Duplex operation. 0 = Half Duplex operation. 7 COLLISION TEST 0, RW Collision Test: 1 = Collision test enabled. 0 = Normal operation.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Table 6-10. Basic Mode Status Register (BMSR), address 0x01h (continued) Bit Bit Name Default 1 JABBER DETECT 0, RO/LH Description Jabber Detect: This bit only has meaning in 10 Mb/s mode. 1 = Jabber condition detected. 0 = No Jabber.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Table 6-13. Negotiation Advertisement Register (ANAR), address 0x04h (continued) Bit Bit Name Default 13 RF 0, RW Description Remote Fault: 1 = Advertises that this device has detected a Remote Fault. 0 = No Remote Fault detected.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Table 6-13. Negotiation Advertisement Register (ANAR), address 0x04h (continued) Bit Bit Name Default 4:0 SELECTOR <00001>, RW Description Protocol Selection Bits: These bits contain the binary encoded protocol selector supported by this port. <00001> indicates that this device supports IEEE 802.3. 6.6.1.1.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com 6.6.1.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 6-15. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05h Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 1 = Link Partner desires Next Page Transfer. 0 = Link Partner does not desire Next Page Transfer.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 6.6.1.1.8 Auto-Negotiate Expansion Register (ANER) This register contains additional Local Device and Link Partner status information. Table 6-16. Auto-Negotiate Expansion Register (ANER), address 0x06h Bit Bit Name Default 15:5 RESERVED 0, RO RESERVED: Writes ignored, Read as 0. Description 4 PDF 0, RO Parallel Detection Fault: 1 = A fault has been detected through the Parallel Detection function.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Table 6-17. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07h (continued) Bit Bit Name 10:0 CODE Default Description <000 0000 0001>, RW Code: This field represents the code field of the next page transmission. If the MP bit is set (bit 13 of this register), then the code shall be interpreted as a "Message Page”, as defined in annex 28C of IEEE 802.3.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Table 6-18. PHY Status Register (PHYSTS), address 10h (continued) Bit Bit Name Default 8 PAGE RECEIVED 0, RO Description Link Code Word Page Received: This is a duplicate of the Page Received bit in the ANER register, but this bit will not be cleared upon a read of the PHYSTS register. 1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address 06h, bit 1).
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com 6.6.1.2.2 MII Interrupt Control Register (MICR) This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy Detect State Change, Link State Change, Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or any of the counters becoming half-full.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Table 6-20. MII Interrupt Status and Misc. Control Register (MISR), address 0x12h (continued) Bit Bit Name Default 10 ANC_INT 0, RO/COR Description Auto-Negotiation Complete interrupt: 1 = Auto-negotiation complete interrupt is pending and is cleared by the current read. 0 = No Auto-negotiation complete interrupt pending.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com 6.6.1.2.6 100 Mb/s PCS Configuration and Status Register (PCSR) This register contains control and status information for the 100BASE Physical Coding Sublayer. Table 6-23.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 6.6.1.2.7 RMII and Bypass Register (RBR) This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed. Table 6-24. RMII and Bypass Register (RBR), addresses 0x17h Bit Bit Name Default 15:6 RESERVED 0, RO 5 RMII_MODE Strap, RW Description RESERVED: Writes ignored, read as 0. Reduced MII Mode: 0 = Standard MII Mode. 1 = Reduced MII Mode.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com 6.6.1.2.9 PHY Control Register (PHYCR) This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address. It also provides Pause Negotiation status. Table 6-26. PHY Control Register (PHYCR), address 0x19h Bit Bit Name Default 15 MDIX_EN Strap, RW Description Auto-MDIX Enable: 1 = Enable Auto-neg Auto-MDIX capability. 0 = Disable Auto-neg Auto-MDIX capability.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Table 6-26.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Table 6-27. 10Base-T Status/Control Register (10BTSCR), address 1Ah (continued) Bit Bit Name Default 3 RESERVED 0, RW RESERVED: Must be zero. Description 2 RESERVED 1, RW RESERVED: Must be set to one. 1 HEARTBEAT_DIS 0, RW Heartbeat Disable: This bit only has influence in half-duplex 10Mb mode. 1 = Heartbeat function disabled. 0 = Heartbeat function enabled.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 6.6.1.2.12 Energy Detect Control (EDCR) This register provides control and status for the Energy Detect function. Table 6-29. Energy Detect Control (EDCR), address 0x1Dh Bit Bit Name Default 15 ED_EN 0, RW Description Energy Detect Enable: Allow Energy Detect Mode.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com 7 Application, Implementation, and Layout NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 7.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Vdd TPRDM Vdd COMMON MODE CHOKES MAY BE REQUIRED 49.9 : 0.1 PF 49.9 : 1:1 TDRDP RD0.1 PF* RD+ TDTD+ TPTDM 0.1 PF* Vdd 49.9 : 1:1 0.1 PF 49.9 : T1 RJ45 NOTE: CENTER TAP IS PULLED TO VDD *PLACE CAPACITORS CLOSE TO THE TRANSFORMER CENTER TAPS TPTDP All values are typical and are +/- 1% PLACE RESISTORS AND CAPACITORS CLOSE TO THE DEVICE Figure 7-2. 10/100 Mb/s Twisted Pair Interface 7.2.1.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Figure 7-3. Crystal Oscillator Circuit Table 7-1.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 Figure 7-4. Power Feedback Connection 7.2.1.3.1 Power Down and Interrupt The Power Down and Interrupt functions are multiplexed on pin 7 of the device. By default, this pin functions as a power-down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR (0x11h) will configure the pin as an active low interrupt output. 7.2.1.3.1.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com Table 7-4. Magnetics Requirements PARAMETER TYP UNITS Turn Ratio 1:1 — ±2% Insertion Loss -1 dB 1-100 MHz -16 dB 1-30 MHz -12 dB 30-60 MHz 10 dB 60-80 MHz -30 dB 1-50MHz -20 dB 50-150 MHz -35 dB 30 MHz -30 dB 60 MHz 1,500 Vrms HPOT Return Loss Differential to Common Rejection Ratio Crosstalk Isolation 7.2.1.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 7.2.2.2.1 Microstrip Impedance - Single-Ended 87 H p Zo = F G ln l5.98 0.8 W + T ¥Er + (1.41) (3) Figure 7-5. Microstrip Impedance - Single-Ended 7.2.2.2.2 Stripline Impedance – Single Ended 60 2 ×H+T pG Zo = F G ln F1.98 × l 0.8 × W + T ¥Er (4) Figure 7-6.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 www.ti.com 7.2.2.2.3 Microstrip Impedance - Differential S @F0.96 A H pG Zdiff = 2 × Zo × F1 F 0.48 le (5) Figure 7-7. Microstrip Impedance - Differential 7.2.2.2.4 Stripline Impedance - Differential Zdiff = 2 × Zo F1 F 0.347 le S @F2.9 A H pG (6) Figure 7-8.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com 7.2.3 SNLS266E – MAY 2007 – REVISED MARCH 2015 Application Curves Figure 7-9. Sample 100 Mb/s Waveform (MLT-3) Figure 7-10.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 7.3 www.ti.com Layout 7.3.1 Layout Guidelines 7.3.1.1 PCB Layout Considerations Place the 49.9-Ω,1% resistors and 0.1-μF decoupling capacitor near the PHYTER TD± and RD± pins and via directly to the Vdd plane. Stubs should be avoided on all signal traces, especially the differential signal pairs. See Figure 7-11.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com 7.3.1.2 SNLS266E – MAY 2007 – REVISED MARCH 2015 PCB Layer Stacking To meet signal integrity and performance requirements, at minimum a four layer PCB is recommended for implementing PHYTER components in end user systems. The following layer stack-ups are recommended for four, six, and eight-layer boards, although other options are possible. Figure 7-13.
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DP83848C, DP83848I DP83848VYB, DP83848YB SNLS266E – MAY 2007 – REVISED MARCH 2015 7.3.2 www.ti.com Layout Example Plane Coupling Component Transformer (if not Integrated in RJ45) PHY Component Termination Components RJ45 Connector Plane Coupling Component Note:Power/ Ground Planes Voided under Transformer System Power/Ground Planes Chassis Ground Plane Figure 7-15. Layout Example 7.4 Power Supply Recommendations The device Vdd supply pins should be bypassed with low impedance 0.
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DP83848C, DP83848I DP83848VYB, DP83848YB www.ti.com SNLS266E – MAY 2007 – REVISED MARCH 2015 8 Device and Documentation Support 8.1 Documentation Support 8.1.1 Related Documentation • • 8.2 AN-1548 PHYTER 100 Base-TX Reference Clock Jitter Tolerance, (SNLA091) AN-1405 DP83848 Single 10/100 Mb/s Ethernet Transceiver Reduced Media Independent Interface (RMII) Mode Application Report, (SNLA076) Related Links The table below lists quick access links.
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PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2014 PACKAGING INFORMATION Orderable Device Status (1) DP83848VYB/NOPB ACTIVE Package Type Package Pins Package Drawing Qty HLQFP PTB 48 250 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) -40 to 105 DP83848 VYB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.