Specifications

DP83848Q-Q1
www.ti.com SNLS341C –MARCH 2011–REVISED MARCH 2015
3.8 Strap Options
The DP83848Q-Q1 uses many of the functional pins as strap options. The values of these pins are
sampled during reset and used to strap the device into specific modes of operation. The strap option pin
assignments are defined below. The functional pin name is indicated in parentheses.
A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default strap option. If the default
option is required, then there is no need for external pullup or pulldown resistors. Because these pins may
have alternate functions after reset is deasserted, they should not be connected directly to V
CC
or GND.
SIGNAL NAME TYPE PIN NO. DESCRIPTION
PHYAD0 (COL) S, O, PU 35 PHY ADDRESS [4:0]: The DP83848Q-Q1 provides five PHY address pins,
PHYAD1 (RXD1_0) S, O, PD 36 the state of which are latched into the PHYCTRL register at system Hardware-
PHYAD2 (RXD0_1) 37 Reset.
PHYAD3 (RXD1_2) 38 The DP83848Q-Q1 supports PHY Address strapping values 0 (<00000>)
PHYAD4 (RXD1_3) 39 through 31 (<11111>).A PHY Adress of 0 puts the part into the Mll isolate
Mode. The Mll isolate mode must be selected by strapping Phy Address 0;
changing to Address 0 by register write will not put the Phy in the Mll isolate
mode. Refer to Section 5.4.4 for additional information.
PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-down resistors.
AN_0 (LED_LINK) S, O, PU 22 AN0: This input pin controls the advertised operating mode of the DP83848Q-
Q1 according to the following table. The value on this pin is set by connecting
the input pin to GND (0) or V
CC
(1) through 2.2 kΩ resistors. This pin should
NEVER be connected directly to GND or V
CC
.
The value set at this input is latched into the DP83848Q-Q1 at Hardware-
Reset.
The float/pull-down status of this pin is latched into the Basic Mode Control
Register and the Auto_Negotiation Advertisement Register during Hardware-
Reset.
The default is 1 because the this pin has an internal pull-up.
AN0 Advertised Mode
0 10BASE-T, Half-Duplex,
100BASE-TX, Half-Duplex
1 10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
MII_MODE (RX_DV) S, O, PD 32 MII MODE SELECT: This strapping option determines the operating mode of
the MAC Data Interface. Default operation (No pull-ups) will enable normal MII
Mode of operation. Strapping MII_MODE high will cause the device to be in
the RMII mode of operation. Because the pin includes an internal pull-down,
the default value is 0.
The following table details the configurations:
MII_MODE MAC Interface Mode
0 MII Mode
1 RMII Mode
LED_CFG (CRS/CRS_DV) S, O, PU 33 LED CONFIGURATION: This strapping option determines the mode of
operation of the LED pin. Default is Mode 1. Mode 1 and Mode 2 can be
controlled via the strap option. All modes are configurable via register access.
See Table 5-2 for LED Mode Selection.
MDIX_EN (RX_ER) S, O, PU 34 MDIX ENABLE: Default is to enable MDIX. This strapping option disables
Auto-MDIX. An external pull-down will disable Auto-MDIX mode.
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