Specifications

DP83848Q-Q1
SNLS341C –MARCH 2011–REVISED MARCH 2015 www.ti.com
Figure 6-2. 10/100-Mb/s Twisted-Pair Interface
6.2.1.2 Clock IN (X1) Requirements
The DP83848Q-Q1 supports an external CMOS level oscillator source or a crystal resonator device.
Oscillator
If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating.
Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 6-1
and Table 6-2.
Crystal
A 25-MHz, parallel, 20-pF load crystal resonator should be used if a crystal source is desired. Figure 6-4
shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the
crystal vendors; check with the vendor for the recommended loads.
The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of
100 mW and a maximum of 500 µW. If a crystal is specified for a lower drive level, a current limiting
resistor should be placed in series between X2 and the crystal.
As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, C
L1
and C
L2
should be set at 33 pF, and R
1
should be set at 0 Ω.
Specification for 25-MHz crystal are listed in Table 6-3.
Figure 6-3. Crystal Oscillator Circuit
64 Application and Implementation Copyright © 2011–2015, Texas Instruments Incorporated
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