Specifications
DP83848Q-Q1
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SNLS341C –MARCH 2011–REVISED MARCH 2015
5.6.2.7 PHY Control Register (PHYCR)
This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address.
It also provides Pause Negotiation status.
Table 5-24. PHY Control Register (PHYCR), address 0x19h
BIT BIT NAME DEFAULT DESCRIPTION
15 MDIX_EN Strap, RW Auto-MDIX Enable:
1 = Enable Auto-neg Auto-MDIX capability.
0 = Disable Auto-neg Auto-MDIX capability.
The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in
the BMCR register to be set. If Auto-Negotiation is not enabled, Auto-
MDIX should be disabled as well.
14 FORCE_MDIX 0, RW Force MDIX:
1 = Force MDI pairs to cross.
(Receive on TPTD pair, Transmit on TPRD pair)
0 = Normal operation.
13 PAUSE_RX 0, RO Pause Receive Negotiated:
Indicates that pause receive should be enabled in the MAC. Based on
ANAR[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table
28B-3, “Pause Resolution”, only if the Auto-Negotiated Highest Common
Denominator is a full duplex technology.
12 PAUSE_TX 0, RO Pause Transmit Negotiated:
Indicates that pause transmit should be enabled in the MAC. Based on
ANAR[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table
28B-3, Pause Resolution, only if the Auto-Negotiated Highest Common
Denominator is a full duplex technology.
11 BIST_FE 0, RW/SC BIST Force Error:
1 = Force BIST Error.
0 = Normal operation.
This bit forces a single error, and is self clearing.
10 PSR_15 0, RW BIST Sequence select:
1 = PSR15 selected.
0 = PSR9 selected.
9 BIST_STATUS 0, LL/RO BIST Test Status:
1 = BIST pass.
0 = BIST fail. Latched, cleared when BIST is stopped.
For a count number of BIST errors, see the BIST Error Count in the
Table 5-26.
8 BIST_START 0, RW BIST Start:
1 = BIST start.
0 = BIST stop.
7 BP_STRETCH 0, RW Bypass LED Stretching:
This will bypass the LED stretching and the LED will reflect the internal
value.
1 = Bypass LED stretching.
0 = Normal operation.
6 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
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