Specifications

DP83848Q-Q1
SNLS341C MARCH 2011REVISED MARCH 2015
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Table 5-18. PHY Status Register (PHYSTS), address 10h (continued)
BIT BIT NAME DEFAULT DESCRIPTION
5 JABBER DETECT 0, RO Jabber Detect: This bit only has meaning in 10 Mb/s mode.
This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that
it is not cleared upon a read of the PHYSTS register.
1 = Jabber condition detected.
0 = No Jabber.
4 AUTO-NEG COMPLETE 0, RO Auto-Negotiation Complete:
1 = Auto-Negotiation complete.
0 = Auto-Negotiation not complete.
3 LOOPBACK STATUS 0, RO Loopback:
1 = Loopback enabled.
0 = Normal operation.
2 DUPLEX STATUS 0, RO Duplex:
This bit indicates duplex status and is determined from Auto-Negotiation or
Forced Modes.
1 = Full duplex mode.
0 = Half duplex mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete and
there is a valid link or if Auto-Negotiation is disabled and there is a valid link.
1 SPEED STATUS 0, RO Speed10:
This bit indicates the status of the speed and is determined from Auto-
Negotiation or Forced Modes.
1 = 10 Mb/s mode.
0 = 100 Mb/s mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete and
there is a valid link or if Auto-Negotiation is disabled and there is a valid link.
0 LINK STATUS 0, RO Link Status:
This bit is a duplicate of the Link Status bit in the BMSR register, except that it
will not be cleared upon a read of the PHYSTS register.
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
5.6.2.2 False Carrier Sense Counter Register (FCSCR)
This counter provides information required to implement the “False Carriers” attribute within the MAU
managed object class of Clause 30 of the IEEE 802.3u specification.
Table 5-19. False Carrier Sense Counter Register (FCSCR), address 0x14h
BIT BIT NAME DEFAULT DESCRIPTION
15:8 RESERVED 0, RO RESERVED: Writes ignored, read as 0
7:0 FCSCNT[7:0] 0, RO/COR False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This counter sticks when
it reaches its max count (FFh).
56 Detailed Description Copyright © 2011–2015, Texas Instruments Incorporated
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