Specifications

DP83848Q-Q1
www.ti.com SNLS341C –MARCH 2011–REVISED MARCH 2015
5.6.2 Extended Registers
5.6.2.1 PHY Status Register (PHYSTS)
This register provides a single location within the register set for quick access to commonly accessed
information.
Table 5-18. PHY Status Register (PHYSTS), address 10h
BIT BIT NAME DEFAULT DESCRIPTION
15 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
14 MDIX MODE 0, RO MDIX mode as reported by the Auto-Negotiation logic:
This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits
in the PHYCR register. When MDIX is enabled, but not forced, this bit will
update dynamically as the Auto-MDIX algorithm swaps between MDI and MDIX
configurations.
1 = MDI pairs swapped
(Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal
(Receive on TRD pair, Transmit on TPTD pair)
13 RECEIVE ERROR 0, RO/LH Receive Error Latch:
LATCH
This bit will be cleared upon a read of the RECR register.
1 = Receive error event has occurred since last read of RXERCNT (address
15h, Page 0).
0 = No receive error event has occurred.
12 POLARITY STATUS 0, RO Polarity Status:
This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared
upon a read of the 10BTSCR register, but not upon a read of the PHYSTS
register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
11 FALSE CARRIER SENSE 0, RO/LH False Carrier Sense Latch:
LATCH
This bit will be cleared upon a read of the FCSR register.
1 = False Carrier event has occurred since last read of FCSCR (address 14h).
0 = No False Carrier event has occurred.
10 SIGNAL DETECT 0, RO/LL 100Base-TX qualified Signal Detect from PMA:
This is the SD that goes into the link monitor. It is the AND of raw SD and
descrambler lock, when address 16h, bit 8 (page 0) is set. When this bit is
cleared, it will be equivalent to the raw SD from the PMD.
9 DESCRAMBLER LOCK 0, RO/LL 100Base-TX Descrambler Lock from PMD.
8 PAGE RECEIVED 0, RO Link Code Word Page Received:
This is a duplicate of the Page Received bit in the ANER register, but this bit
will not be cleared upon a read of the PHYSTS register.
1 = A new Link Code Word Page has been received. Cleared on read of the
ANER (address 06h, bit 1).
0 = Link Code Word Page has not been received.
7 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
6 REMOTE FAULT 0, RO Remote Fault:
1 = Remote Fault condition detected (cleared on read of BMSR (address 01h)
register or by reset). Fault criteria: notification from Link Partner of Remote
Fault via Auto-Negotiation.
0 = No remote fault condition detected.
Copyright © 2011–2015, Texas Instruments Incorporated Detailed Description 55
Submit Documentation Feedback
Product Folder Links: DP83848Q-Q1