Specifications
DP83848Q-Q1
SNLS341C –MARCH 2011–REVISED MARCH 2015
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Table 5-8. Register Table
Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Basic Mode 00h BMCR Reset Loopback Speed Auto-Neg Power Isolate Restart Duplex Collision Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Control Register Selection Enable Down Auto-Neg Mode Test
Basic Mode Status 01h BMSR 100Base- 100Base- 100Base- 10Base-T 10Base-T Reserved Reserved Reserved Reserved MF Auto-Neg Remote Auto-Neg Link Jabber Detect Extended
Register T4 TX FDX TX HDX Preamble Fault Capability
FDX HDX Complete Ability Status
Suppress
PHY Identifier 02h PHYIDR1 OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB
Register 1
PHY Identifier 03h PHYIDR2 OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB VNDR_ VNDR_ VNDR_ VNDR_ VNDR_ VNDR_ MDL_ MDL_ MDL_ MDL_
Register 2
MDL MDL MDL MDL MDL MDL REV REV REV REV
Auto-Negotiation 04h ANAR Next Page Reserved Remote Reserved ASM_DIR PAUSE T4 TX_FD TX 10_FD 10 Protocol Protocol Protocol Protocol Protocol
Advertisement Ind Fault Selection Selection Selection Selection Selection
Register
Auto-Negotiation 05h ANLPAR Next Page ACK Remote Reserved ASM_DIR PAUSE T4 TX_FD TX 10_FD 10 Protocol Protocol Protocol Protocol Protocol
Link Partner Ability Ind Fault Selection Selection Selection Selection Selection
Register (Base
Page)
Auto-Negotiation 05h ANLPARN Next Page ACK Message ACK2 Toggle Code Code Code Code Code Code Code Code Code Code Code
Link Partner Ability P Ind Page
Register (Next
Page)
Auto-Negotiation 06h ANER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PDF LP_NP_ NP_ PAGE_ LP_AN_
Expansion
ABLE ABLE RX ABLE
Register
Auto-Negotiation 07h ANNPTR Next Page Reserved Message ACK2 TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE
Next Page TX Ind Page
Register
RESERVED 08-0fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
EXTENDED REGISTERS
PHY Status 10h PHYSTS Reserved MDIX Rx Err Polarity False Signal Descrambl Page Reserved Remote Jabber Detect Auto-Neg Loopback Duplex Speed Status Link
Register mode Latch Status Carrier Detect er Lock Fault Status Status
Receive Complete Status
Sense
RESERVED 11–13h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
False Carrier 14h FCSCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT
Sense Counter
Register
Receive Error 15h RECR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT
Counter Register
PCS Sub-Layer 16h PCSR Reserved Reserved Reserved Reserved FREE_CLK TQ_EN SD_FORC SD_ DESC_TIM Reserved FORCE_ Reserved Reserved NRZI_ SCRAM_ DE
Configuration and E_PMA E
OPTION 100_OK BYPASS BYPASS SCRAM_B
Status Register
YPASS
RMII and Bypass 17h RBR SIM_WRIT Reserved DIS_TX_O RX_PORT RX_PORT TX_SOUR TX_SOUR PMD_LOO SCMII_RX SCMII_TX RMII_MODE RMII_REV RX_OVF_ST RX_UNF_S ELAST_BUF ELAST_BU
Register E PT CE CE P 1_0 S TS F
LED Direct Control 18h LEDCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DRV_LNKL Reserved Reserved LNKLED Reserved
Register ED
PHY Control 19h PHYCR MDIX_EN FORCE_M PAUSE_R PAUSE_TX BIST_FE PSR_15 BIST_ BIST_STA BP_STRET Reserved LED_ PHY PHY PHY PHY PHY
Register DIX X RT CH
STATUS CFG ADDR ADDR ADDR ADDR ADDR
10Base-T 1Ah 10BT_SER Reserved Reserved Reserved Reserved SQUELCH SQUELCH SQUELCH LOOPBAC LP_DIS FORCE_ Reserved POLARITY Reserved Reserved HEARTBEAT JABBER_D
Status/Control IAL K_10_DIS _DIS IS
LINK_10
Register
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