Specifications

DP83848Q-Q1

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SNLS341C –MARCH 2011–REVISED MARCH 2015

5.5.1.3.10 Receiver

The decoder detects the end of a frame when no additional mid-bit transitions are detected. Within one

and a half bit times after the last bit, carrier sense is de-asserted. Receive clock stays active for five more

bit times after CRS goes low, to ensure the receive timings of the controller.

5.6 Memory

Table 5-7. Register Map

OFFSET

ACCESS TAG DESCRIPTION

HEX DECIMAL

00h 0 RW BMCR Basic Mode Control Register

01h 1 RO BMSR Basic Mode Status Register

02h 2 RO PHYIDR1 PHY Identifier Register #1

03h 3 RO PHYIDR2 PHY Identifier Register #2

04h 4 RW ANAR Auto-Negotiation Advertisement Register

05h 5 RW ANLPAR Auto-Negotiation Link Partner Ability Register (Base Page)

05h 5 RW ANLPARNP Auto-Negotiation Link Partner Ability Register (Next Page)

06h 6 RW ANER Auto-Negotiation Expansion Register

07h 7 RW ANNPTR Auto-Negotiation Next Page TX

08h - Fh 8 - 15 RESERVED RESERVED

EXTENDED REGISTERS

10h 16 RO PHYSTS PHY Status Register

11h - 13h 17 - 19 RO RESERVED RESERVED

14h 20 RO FCSCR False Carrier Sense Counter Register

15h 21 RO RECR Receive Error Counter Register

16h 22 RW PCSR PCS Sub-Layer Configuration and Status Register

17h 23 RW RBR RMII and Bypass Register

18h 24 RW LEDCR LED Direct Control Register

19h 25 RW PHYCR PHY Control Register

1Ah 26 RW 10BTSCR 10Base-T Status/Control Register

1Bh 27 RW CDCTRL1 CD Test Control Register and BIST Extensions Register

1Ch 28 RW RESERVED RESERVED

1Dh 29 RW EDCR Energy Detect Control Register

1Eh - 1Fh 30 - 31 RW RESERVED RESERVED

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