Specifications

DP83848Q-Q1

SNLS341C –MARCH 2011–REVISED MARCH 2015

www.ti.com

5.5.1.2.9 4B/5B Decoder

The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B

nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and

replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble

pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the

duration of the entire packet. This conversion ceases upon the detection of the T/R code-group pair

denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.

5.5.1.2.10 100BASE-TX Link Integrity Monitor

The 100 Base TX Link monitor ensures that a valid and stable link is established before enabling both the

Transmit and Receive PCS layer.

Signal detect must be valid for 395us to allow the link monitor to enter the 'Link Up' state, and enable the

transmit and receive functions.

5.5.1.2.11 Bad SSD Detection

A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle

code-groups which is not prefixed by the code-group pair /J/K.

If this condition is detected, the DP83848Q-Q1 will assert RX_ER and present RXD[3:0] = 1110 to the MII

for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are

detected. In addition, the False Carrier Sense Counter register (FCSCR) will be incremented by one.

Once at least two IDLE code groups are detected, RX_ER and CRS become de-asserted.

5.5.1.3 10BASE-T Transceiver Module

The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision,

heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not

required on the 10BASE-T interface because this is integrated inside the DP83848Q-Q1 . This section

focuses on the general 10BASE-T system level operation.

5.5.1.3.1 Operational Modes

The DP83848Q-Q1 has two basic 10BASE-T operational modes:

• Half Duplex mode

• Full Duplex mode

5.5.1.3.1.1 Half Duplex Mode

In Half Duplex mode the DP83848Q-Q1 functions as a standard IEEE 802.3 10BASE-T transceiver

supporting the CSMA/CD protocol.

5.5.1.3.1.2 Full Duplex Mode

In Full Duplex mode the DP83848Q-Q1 can simultaneously transmit and receive without asserting the

collision signal. The 10 Mb/s ENDEC is designed to encode and decode simultaneously.

5.5.1.3.2 Smart Squelch

The smart squelch is responsible for determining when valid data is present on the differential receive

inputs. The DP83848Q-Q1 implements an intelligent receive squelch to ensure that impulse noise on the

receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the

10BASE-T operational mode.

The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the

IEEE 802.3 10BSE-T standard) to determine the validity of data on the twisted-pair inputs (see Figure 5-

9).

Submit Documentation Feedback

Product Folder Links: DP83848Q-Q1