Specifications

DP83848Q-Q1
www.ti.com SNLS341C –MARCH 2011–REVISED MARCH 2015
The digital oscilloscope plot provided in Figure 5-9 illustrates the severity of the BLW event that can
theoretically be generated during 100BASE-TX packet transmission. This event consists of approximately
800 mV of DC offset for a period of 120 ms. Left uncompensated, events such as this can cause packet
loss.
5.5.1.2.3 Signal Detect
The signal detect function of the DP83848Q-Q1 is incorporated to meet the specifications mandated by
the ANSI FDDI TP-PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage
thresholds and timing parameters.
Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3u Auto-
Negotiation by the 100BASE-TX receiver do not cause the DP83848Q-Q1 to assert signal detect.
5.5.1.2.4 MLT-3 to NRZI Decoder
The DP83848Q-Q1 decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary
NRZI data.
5.5.1.2.5 NRZI to NRZ
In a typical application, the NRZI to NRZ decoder is required in order to present NRZ formatted data to the
descrambler.
5.5.1.2.6 Serial to Parallel
The 100BASE-TX receiver includes a Serial to Parallel converter which supplies 5-bit wide data symbols
to the PCS Rx state machine.
5.5.1.2.7 Descrambler
A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an
identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the
scrambled data (SD) as represented in the equations:
(1)
Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the
knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the
descrambler has recognized 12 consecutive IDLE code-groups, where an unscrambled IDLE code-group
in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and
generate unscrambled data in the form of unaligned 5B code-groups.
In order to maintain synchronization, the descrambler must continuously monitor the validity of the
unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to
constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer
starts a 722 µs countdown. Upon detection of sufficient IDLE code-groups (58 bit times) within the 722 µs
period, the hold timer will reset and begin a new countdown. This monitoring operation will continue
indefinitely given a properly operating network connection with good signal integrity. If the line state
monitor does not recognize sufficient unscrambled IDLE code-groups within the 722 µs period, the entire
descrambler will be forced out of the current state of synchronization and reset in order to re-acquire
synchronization.
5.5.1.2.8 Code-group Alignment
The code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the
descrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5
bits). Code-group alignment occurs after the J/K code-group pair is detected. Once the J/K code-group
pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary.
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