Specifications

DP83848Q-Q1
SNLS341C –MARCH 2011–REVISED MARCH 2015 www.ti.com
3 Pin Configuration and Functions
The DP83848Q-Q1 pins are classified into the following interface categories (each interface is described
in the sections that follow):
• Serial Management Interface
• MAC Data Interface
• Clock Interface
• LED Interface
• Reset
• Strap Options
• 10/100 Mb/s PMD Interface
• Special Connect Pins
• Power and Ground pins
All DP83848Q-Q1 signal pins are I/O cells regardless of the particular use. The definitions below define
the functionality of the I/O cells for each pin.
NOTE
Strapping pin option. See Section 3.8 for strap definitions.
Type: I Input
Type: O Output
Type: I/O Input/Output
Type: OD Open Drain
Type: PD,PU Internal Pulldown/Pullup
Type: S Strapping Pin (All strap pins have weak internal pull-ups or pull-downs. If the default strap
value is to be changed then an external 2.2-kΩ resistor should be used. See Section 3.8 for
details.)
4 Pin Configuration and Functions Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83848Q-Q1