Specifications

DP83848Q-Q1

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SNLS341C –MARCH 2011–REVISED MARCH 2015

The DP83848Q-Q1 can Auto-Negotiate or parallel detect to a specific technology depending on the

receive signal at the PMD input pair. A valid link can be established for the receiver even when the

DP83848Q-Q1 is in Isolate mode.

5.4.5 Half Duplex vs. Full Duplex

The DP83848Q-Q1 supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds.

Half-duplex relies on the CSMA/CD protocol to handle collisions and network access. In Half-Duplex

mode, CRS responds to both transmit and receive activity in order to maintain compliance with the IEEE

802.3 specification.

Because the DP83848Q-Q1 is designed to support simultaneous transmit and receive activity, it is

capable of supporting full-duplex switched applications with a throughput of up to 200 Mb/s per port when

operating in 100BASE-TX. CSMA/CD protocol does not apply to full-duplex operation so DP83848Q-Q1

disables its own internal collision sensing and reporting functions and modifies the behavior of Carrier

Sense (CRS) such that it indicates only receive activity. This allows a full-duplex capable MAC to operate

properly.

All modes of operation (100BASE-TX and 10BASE-T) can run either half-duplex or full-duplex.

Additionally, other than CRS and Collision reporting, all remaining MII signaling remains the same

regardless of the selected duplex mode.

It is important to understand that while Auto-Negotiation with the use of Fast Link Pulse code words can

interpret and configure to full-duplex operation, parallel detection can not recognize the difference between

full and half-duplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. As specified in the

802.3u specification, if a far-end link partner is configured to a forced full duplex 100BASE-TX ability, the

parallel detection state machine in the partner would be unable to detect the full duplex capability of the

far-end link partner. This link segment would negotiate to a half duplex 100BASE-TX configuration (same

scenario for 10 Mb/s).

5.4.6 Reset Operation

The DP83848Q-Q1 includes an internal power-on reset (POR) function and does not need to be explicitly

reset for normal operation after power up. If required during normal operation, the device can be reset by

a hardware or software reset.

5.4.6.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 µs, to

the RESET_N pin. This will reset the device such that all registers will be reinitialized to default values and

the hardware configuration values will be re-latched into the device (similar to the power-up/reset

operation).

5.4.6.2 Software Reset

A software reset is accomplished by setting the reset bit (bit 15) of the Basic Mode Control Register

(BMCR). The period from the point in time when the reset bit is set to the point in time when software

reset has concluded is approximately 1 µs.

A software reset will reset the device such that all the registers will be re-initialized to default values and

the hardware configuration values will be re-latched into the device. Software driver code must wait 3 µs

following a software reset before allowing further serial MII operations with the DP83848Q-Q1

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