Specifications

DP83848Q-Q1
SNLS341C –MARCH 2011–REVISED MARCH 2015 www.ti.com
For transmit VOD testing, the Packet BIST Continuous Mode can be used to allow continuous data
transmission, setting BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh).
The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 (0x1Bh), bits
[15:8].
5.3.6 Energy Detect Mode
When Energy Detect is enabled and there is no activity on the cable, the DP83848Q-Q1 will remain in a
low power mode while monitoring the transmission line. Activity on the line will cause the DP83848Q-Q1
to go through a normal power up sequence. Regardless of cable activity, the DP83848Q-Q1 will
occasionally wake up the transmitter to put ED pulses on the line, but will otherwise draw as little power as
possible. Energy detect functionality is controlled via register Energy Detect Control (EDCR), address
0x1Dh.
5.4 Device Functional Modes
The DP83848Q-Q1 supports two modes of operation using the MII interface pins. The options are defined
in the following sections and include:
• MII Mode
• RMII Mode
The modes of operation can be selected by strap options or register control. For RMII mode, it is required
to use the strap option, because it requires a 50 MHz clock instead of the normal 25 MHz.
In each of these modes, the IEEE 802.3 serial management interface is operational for device
configuration and status. The serial management interface of the MII allows for the configuration and
control of multiple PHY devices, gathering of status, error information, and the determination of the type
and capabilities of the attached PHY(s).
5.4.1 MII Interface
The DP83848Q-Q1 incorporates the Media Independent Interface (MII) as specified in Clause 22 of the
IEEE 802.3u standard. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s
systems. This section describes the nibble wide MII data interface.
The nibble wide MII data interface consists of a receive bus and a transmit bus each with control signals
to facilitate data transfer between the PHY and the upper layer (MAC).
5.4.1.1 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the Media Independent Interface. This interface
includes a dedicated receive bus and a dedicated transmit bus. These two data buses, along with various
control and status signals, allow for the simultaneous exchange of data between the DP83848Q-Q1 and
the upper layer agent (MAC).
The receive interface consists of a nibble wide data bus RXD[3:0], a receive error signal RX_ER, a receive
data valid flag RX_DV, and a receive clock RX_CLK for synchronous transfer of the data. The receive
clock operates at either 2.5 MHz to support 10 Mb/s operation modes or at 25 MHz to support 100 Mb/s
operational modes.
The transmit interface consists of a nibble wide data bus TXD[3:0], a transmit enable control signal
TX_EN, and a transmit clock TX_CLK which runs at either 2.5 MHz or 25 MHz.
Additionally, the MII includes the carrier sense signal CRS, as well as a collision detect signal COL. The
CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in
Half Duplex mode. The COL signal asserts as an indication of a collision which can occur during half-
duplex operation when both a transmit and receive operation occur simultaneously.
30 Detailed Description Copyright © 2011–2015, Texas Instruments Incorporated
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