Specifications

VCC

165:

.2 k:

AN0 = 1

LED

_LINK

DP83848Q-Q1

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SNLS341C –MARCH 2011–REVISED MARCH 2015

Specifically, when the LED output is used to drive the LED directly, the active state of the output driver is

dependent on the logic level sampled by the AN0 input upon power-up/reset. For example, if the AN0

input is resistively pulled low then the output will be configured as an active high driver. Conversely, if the

AN0 input is resistively pulled high, then the output will be configured as an active low driver.

Refer to Figure 5-1 for an example of an AN0 connection to external components. In this example, the

AN0 strapping results in Auto-Negotiation enabled with 10/100 Half/Full-Duplex advertised .

The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual

purpose pins.

Figure 5-1. AN0 Strapping and LED Loading Example

5.3.3.2 LED Direct Control

The DP83848Q-Q1 provides another option to directly control the LED output through the LED Direct

Control Register (LEDCR), address 18h. The register does not provide read access to the LED.

5.3.4 Internal Loopback

The DP83848Q-Q1 includes a Loopback Test mode for facilitating system diagnostics. The Loopback

mode is selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this

bit enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in

bit 3 of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be transmitted onto

the media. To ensure that the desired operating mode is maintained, Auto-Negotiation should be disabled

before selecting the Loopback mode.

5.3.5 BIST

The DP83848Q-Q1 incorporates an internal Built-in Self Test (BIST) circuit to accommodate in-circuit

testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data

paths. BIST testing can be performed with the part in the internal loopback mode or externally looped back

using a loopback cable fixture.

The BIST is implemented with independent transmit and receive paths, with the transmit block generating

a continuous stream of a pseudo random sequence. The user can select a 9 bit or 15 bit pseudo random

sequence from the PSR_15 bit in the PHY Control Register (PHYCR). The received data is compared to

the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the

BIST pass/fail status.

The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit

defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs,

the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit.

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