Specifications

DP83848Q-Q1
SNLS341C –MARCH 2011–REVISED MARCH 2015 www.ti.com
5.3 Feature Description
5.3.1 Auto-Negotiation
The Auto-Negotiation function provides a mechanism for exchanging configuration information between
two ends of a link segment and automatically selecting the highest performance mode of operation
supported by both devices. Fast Link Pulse (FLP) Bursts provide the signalling used to communicate
Auto-Negotiation abilities between two devices at each end of a link segment. For further detail regarding
Auto-Negotiation, refer to Clause 28 of the IEEE 802.3u specification. The DP83848Q-Q1 supports four
different Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex, and 100
Mb/s Full Duplex), so the inclusion of Auto-Negotiation ensures that the highest performance protocol will
be selected based on the advertised ability of the Link Partner. The Auto-Negotiation function within the
DP83848Q-Q1 can be controlled either by internal register access or by the use of the AN0 pin.
5.3.1.1 Auto-Negotiation Pin Control
The state of AN0 determines the specific mode advertised by the DP83848Q-Q1 as given in Table 5-1.
This pin allows configuration options to be selected without requiring internal register access.
The state of AN0 upon power-up/reset, determines the state of bits [8:5] of the ANAR register.
The Auto-Negotiation function selected at power-up or reset can be changed at any time by writing to the
Basic Mode Control Register (BMCR) at address 0x00h.
Table 5-1. Auto-Negotiation Modes
AN0 Advertised Mode
10BASE-T Half-Duplex
0
100BASE-TX, Half-Duplex
10BASE-T, Half/Full-Duplex
1
100BASE-TX, Half/Full-Duplex
5.3.1.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83848Q-Q1 transmits the abilities programmed into the Auto-
Negotiation Advertisement register (ANAR) at address 04h via FLP Bursts. Any combination of 10 Mb/s,
100 Mb/s, Half-Duplex, and Full Duplex modes may be selected.
Auto-Negotiation Priority Resolution:
1. 100BASE-TX Full Duplex (Highest Priority)
2. 100BASE-TX Half Duplex
3. 10BASE-T Full Duplex
4. 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h provides control for enabling, disabling, and
restarting the Auto-Negotiation process. When Auto-Negotiation is disabled, the Speed Selection bit in the
BMCR controls switching between 10 Mb/s or 100 Mb/s operation, and the Duplex Mode bit controls
switching between full duplex operation and half duplex operation. The Speed Selection and Duplex Mode
bits have no effect on the mode of operation when the Auto-Negotiation Enable bit is set.
The Link Speed can be examined through the PHY Status Register (PHYSTS) at address 10h after a Link
is achieved.
The Basic Mode Status Register (BMSR) indicates the set of available abilities for technology types, Auto-
Negotiation ability, and Extended Register Capability. These bits are permanently set to indicate the full
functionality of the DP83848Q-Q1 (only the 100BASE-T4 bit is not set because the DP83848Q-Q1 does
not support that function).
26 Detailed Description Copyright © 2011–2015, Texas Instruments Incorporated
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