Specifications

DP83848Q-Q1
SNLS341C –MARCH 2011–REVISED MARCH 2015 www.ti.com
Electrical Characteristics: AC (continued)
PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT
ISOLATION TIMING (SEE Figure 4-26)
T2.28.1 From software clear of bit 10 in
the BMCR register to the
100 µs
transition from Isolate to Normal
mode
T2.28.2 From Deassertion of S/W or H/W
Reset to transition from Isolate to 500 µs
Normal mode
MHz_OUT TIMING (SEE Figure 4-27)
T2.29.1 25 MHz_OUT High/Low Time MII mode 20 ns
RMII mode 10 ns
T2.29.2 25 MHz_OUT propagation delay Relative to X1 8 ns
100-Mb/s X1 TO TX_CLK TIMING (SEE Figure 4-28)
T2.30.1 X1 to TX_CLK delay
(24)
100 Mb/s Normal mode 0 5 ns
(24) X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data.
Figure 4-1. Power Up Timing
16 Specifications Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83848Q-Q1