Specifications

DP83848Q-Q1
www.ti.com SNLS341C –MARCH 2011–REVISED MARCH 2015
Electrical Characteristics: AC (continued)
PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT
10-Mb/s JABBER TIMING (SEE Figure 4-18)
T2.20.1 Jabber Activation Time 85 ms
T2.20.2 Jabber Deactivation Time 500 ms
10BASE-T NORMAL LINK PULSE TIMING (SEE Figure 4-19)
T2.21.1 Pulse Width 100 ns
T2.21.2 Pulse Period 16 ms
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING (SEE Figure 4-20)
T2.22.1 Clock, Data Pulse Width 100 ns
T2.22.2 Clock Pulse to Clock Pulse
125 µs
Period
T2.22.3 Clock Pulse to Data Pulse Period Data = 1 62 µs
T2.22.4 Burst Width 2 ms
T2.22.5 FLP Burst to FLP Burst Period 16 ms
100BASE-TX SIGNAL DETECT TIMING (SEE Figure 4-21)
T2.23.1 SD Internal Turn-on Time 1 ms
T2.23.2 SD Internal Turn-off Time 350 µs
100-Mb/s INTERNAL LOOPBACK TIMING (SEE Figure 4-22)
TX_EN to RX_DV 100 Mb/s internal loopback mode 240 ns
T2.24.1 Loopback
(18)(19)
10-Mb/s INTERNAL LOOPBACK TIMING (SEE Figure 4-23)
T2.25.1 TX_EN to RX_DV Loopback
(20)
10 Mb/s internal loopback mode 2 µs
RMII TRANSMIT TIMING (SEE Figure 4-24)
T2.26.1 X1 Clock Period 50 MHz Reference Clock 20 ns
T2.26.2 TXD[1:0], TX_EN, Data Setup to
4 ns
X1 rising
T2.26.3 TXD[1:0], TX_EN, Data Hold
2 ns
from X1 rising
T2.26.4 X1 Clock to PMD Output Pair From X1 Rising edge to first bit of
17 bits
Latency symbol
RMII RECEIVE TIMING (SEE Figure 4-25)
T2.27.1 X1 Clock Period 50 MHz Reference Clock 20 ns
T2.27.2 RXD[1:0], CRS_DV, RX_DV and
RX_ER output delay from X1 2 14 ns
rising
(21)(22)
T2.27.3 From JK symbol on PMD Receive
CRS ON delay (100Mb) Pair to initial assertion of 18.5 bits
CRS_DV
(23)
T2.27.4 From TR symbol on PMD Receive
CRS OFF delay (100Mb) Pair to initial deassertion of 27 bits
CRS_DV
(23)
T2.27.5 From symbol on Receive Pair.
RXD[1:0] and RX_ER latency
Elasticity buffer set to default value 38 bits
(100Mb)
(01)
(18) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
(19) Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during
which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the
initial 550µs “dead-time”.
(20) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
(21) Per the RMII Specification, output delays assume a 25pF load.
(22) RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.
(23) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may toggle
synchronously at the end of the packet to indicate CRS deassertion.
Copyright © 2011–2015, Texas Instruments Incorporated Specifications 15
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