Specifications

DP83848Q-Q1
SNLS341C –MARCH 2011–REVISED MARCH 2015 www.ti.com
Electrical Characteristics: AC (continued)
PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT
100BASE-TX TRANSMIT TIMING (t
R/F
AND JITTER) (SEE Figure 4-8)
T2.8.1 100 Mb/s PMD Output Pair t
R
3 4 5 ns
and t
F
100 Mb/s t
R
and t
F
Mismatch
(6)(7)
500 ps
T2.8.2 100 Mb/s PMD Output Pair 1.4 ns
Transmit Jitter
100BASE-TX RECEIVE PACKET LATENCY TIMING (SEE Figure 4-9)
T2.9.1 Carrier Sense ON Delay
(8)(9)(10)
100 Mb/s Normal mode 20 bits
T2.9.2 Receive Data Latency
(9)
100 Mb/s Normal mode 24 bits
100BASE-TX RECEIVE PACKET DEASSERTION TIMING (SEE Figure 4-10)
T2.10.1 Carrier Sense OFF Delay
(11)(12)
100 Mb/s Normal mode 24 bits
10-Mb/s MII TRANSMIT TIMING (SEE Figure 4-11)
T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns
T2.11.2 TXD[3:0], TX_EN Data Setup to
10 Mb/s MII mode 25 ns
TX_CLK fall
(13)
T2.11.3 TXD[3:0], TX_EN Data Hold from
10 Mb/s MII mode 0 ns
TX_CLK rise
(13)
10-Mb/s MII RECEIVE TIMING (SEE Figure 4-12)
T2.12.1 RX_CLK High/Low Time
(14)
160 200 240 ns
T2.12.2 RX_CLK TO RXD[3:0}, RX_DV
10 Mb/s MII mode 100 ns
Delay
T2.12.3 RX_CLK rising edge delay from
10 Mb/s MII mode 100 ns
RXD[3:0], RX_DV Valid
10BASE-T TRANSMIT TIMING (START OF PACKET) (SEE Figure 4-13)
T2.15.1 Transmit Output Delay from the
10 Mb/s MII mode 3.5 bits
Falling Edge of TX_CLK
(15)
10BASE-T TRANSMIT TIMING (END OF PACKET) (SEE Figure 4-14)
T2.16.1 End of Packet High Time (with '0'
250 300 ns
ending bit)
T2.16.2 End of Packet High Time (with '1'
250 300 ns
ending bit)
10BASE-T RECEIVE TIMING (START OF PACKET) (SEE Figure 4-15)
T2.17.1 Carrier Sense Turn On Delay
630 1000 ns
(PMD Input Pair to CRS)
T2.17.2 RX_DV Latency
(16)(17)
10 bits
T2.17.3 Receive Data Latency
(17)
Measurement shown from SFD 8 bits
10BASE-T RECEIVE TIMING (END OF PACKET) (SEE Figure 4-16)
T2.18.1 Carrier Sense Turn Off Delay 1 µs
10-Mb/s HEARTBEAT TIMING (SEE Figure 4-17)
T2.19.1 CD Heartbeat Delay 10 Mb/s half-duplex mode 1200 ns
T2.19.2 CD Heartbeat Duration 10 Mb/s half-duplex mode 1000 ns
(6) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times
(7) Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude
(8) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
(9) 1 bit time = 10 ns in 100 Mb/s mode.
(10) PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
(11) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
(12) 1 bit time = 10 ns in 100 Mb/s mode.
(13) An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on
the falling edge of TX_CLK.
(14) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low
times will not be violated.
(15) 1 bit time = 100 ns in 10 Mb/s.
(16) 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV
(17) 1 bit time = 100 ns in 10 Mb/s mode.
14 Specifications Copyright © 2011–2015, Texas Instruments Incorporated
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