Specifications

DP83848Q-Q1
www.ti.com SNLS341C –MARCH 2011–REVISED MARCH 2015
4.6 Electrical Characteristics: AC
PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT
POWER UP TIMING (SEE Figure 4-1)
T2.1.1 MDIO is pulled high for 32-bit serial
Post Power Up Stabilization time
management initialization
prior to MDC preamble for 167 ms
X1 Clock must be stable for a min.
register accesses
(1)
of 167ms at power up.
T2.1.2 Hardware Configuration Pins are
described in the Pin Description
Hardware Configuration Latch-in
section.
167 ms
Time from power up
(1)
X1 Clock must be stable for a min.
of 167ms at power up.
T2.1.3 Hardware Configuration pins
50 ns
transition to output drivers
RESET TIMING (SEE Figure 4-2)
T2.2.1 Post RESET Stabilization time
MDIO is pulled high for 32-bit serial
prior to MDC preamble for 3 µs
management initialization
register accesses
T2.2.2 Hardware Configuration Latch-in
Hardware Configuration Pins are
Time from the Deassertion of 3 µs
described in Section 3.2
RESET (either soft or hard)
(2)
T2.2.3 Hardware Configuration pins
50 ns
transition to output drivers
T2.2.4 X1 Clock must be stable for at min.
RESET pulse width of 1us during RESET pulse low 1 µs
time.
MII SERIAL MANAGEMENT TIMING (SEE Figure 4-3)
T2.3.1 MDC to MDIO (Output) Delay 0 30 ns
Time
T2.3.2 MDIO (Input) to MDC Setup Time 10 ns
T2.3.3 MDIO (Input) to MDC Hold Time 10 ns
T2.3.4 MDC Frequency 2.5 25 MHz
100-Mb/s MII TRANSMIT TIMING (SEE Figure 4-4)
T2.4.1 TX_CLK High/Low Time 100 Mb/s Normal mode 16 20 24 ns
T2.4.2 TXD[3:0], TX_EN Data Setup to
100 Mb/s Normal mode 10 ns
TX_CLK
T2.4.3 TXD[3:0], TX_EN Data Hold from
100 Mb/s Normal mode 0 ns
TX_CLK
100-Mb/s MII RECEIVE TIMING (SEE Figure 4-5)
T2.5.1 RX_CLK High/Low Time
(3)
100 Mb/s Normal mode 16 20 24 ns
T2.5.2 RX_CLK to RXD[3:0], RX_DV,
100 Mb/s Normal mode 10 30 ns
RX_ER Delay
100BASE-TX MII TRANSMIT PACKET LATENCY TIMING (SEE Figure 4-6)
T2.6.1 TX_CLK to PMD Output Pair 100BASE-TX modes bits
Latency
(4)
100BASE-TX TRANSMIT PACKET DEASSERTION TIMING (SEE Figure 4-7)
T2.7.1 TX_CLK to PMD Output Pair 100BASE-TX mode 5 bits
Deassertion
(5)
(1) In RMII Mode, the minimum Post Power up Stabilization and Hardware Configuration Latch-in times are 84ms.
(2) It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide fast RC time
constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
(3) RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high
and low times will not be violated.
(4) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
(5) Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the
first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
Copyright © 2011–2015, Texas Instruments Incorporated Specifications 13
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