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DP83848Q-Q1

SNLS341C –MARCH 2011–REVISED MARCH 2015

DP83848Q-Q1 PHYTER™ Extended-Temperature, Single-Port 10/100-Mbps Ethernet

Physical Layer Transceiver

1 Device Overview

1.1 Features

• AEC-Q100 Grade 2 • IEEE 802.3u ENDEC, 10BASE-T Transceivers and

Filters

• Extreme Temperature From –40°C to 105°C

• IEEE 802.3u PCS, 100BASE-TX Transceivers and

• Low-Power 3.3-V, 0.18-µm CMOS Technology

Filters

• Low Power Consumption < 270 mW Typical

• Integrated ANSI X3.263 Compliant TP-PMD

• 3.3-V MAC Interface

Physical Sublayer With Adaptive Equalization and

• Auto-MDIX for 10/100 Mb/s

Baseline Wander Compensation

• Energy Detection Mode

• Error-Free Operation up to 150 Meters

• 25-MHz Clock Out

• Programmable LED Support for Link and Activity

• RMII Rev. 1.2 Interface (Configurable)

• Single Register Access for Complete PHY Status

• MII Serial Management Interface (MDC and MDIO)

• 10/100-Mb/s Packet BIST (Built in Self Test)

• IEEE 802.3u MII

• IEEE 802.3u Auto-Negotiation and Parallel

Detection

1.2 Applications

• Automotive and Transportation • General Embedded Applications

• Industrial Controls and Factory Automation

1.3 Description

The number of applications requiring Ethernet connectivity continues to increase, driving Ethernet-enabled

devices into harsher environments.

The DP83848Q-Q1 was designed to meet the challenge of these new applications with an extended

temperature performance that goes beyond the typical Industrial temperature range. The DP83848Q-Q1 is

a highly reliable, feature rich, robust device which meets IEEE 802.3u standards over an extended

temperature range of –40°C to 105°C. This device is ideally suited for harsh environments such as

automotive and transportation, wireless remote base stations, and industrial control applications.

The device offers enhanced ESD protection and the choice of an MII or RMII interface for maximum

flexibility in MPU selection; all in a 40 pin WQFN package.

The DP83848Q-Q1 extends the leadership position of the PHYTER™ family of devices with a wide

operating temperature range. The TI line of PHYTER transceivers builds on decades of Ethernet expertise

to offer the high performance and flexibility that allows the end user an easy implementation tailored to

meet these application needs.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

DP83848Q-Q1 WQFN (40) 6.00 mm × 6.00 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Summary of content (82 pages)

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Product Folder Sample & Buy Tools & Software Technical Documents Support & Community DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 DP83848Q-Q1 PHYTER™ Extended-Temperature, Single-Port 10/100-Mbps Ethernet Physical Layer Transceiver 1 Device Overview 1.1 Features 1 • • • • • • • • • • • • AEC-Q100 Grade 2 Extreme Temperature From –40°C to 105°C Low-Power 3.3-V, 0.18-µm CMOS Technology Low Power Consumption < 270 mW Typical 3.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 1.4 www.ti.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Table of Contents 1 2 3 4 Device Overview ......................................... 1 4.5 Electrical Characteristics: DC ....................... 12 1.1 Features .............................................. 1 4.6 Electrical Characteristics: AC ....................... 13 1.2 Applications ........................................... 1 1.3 Description ............................................ 1 5.1 Overview 1.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com 3 Pin Configuration and Functions The DP83848Q-Q1 pins are classified into the following interface categories (each interface is described in the sections that follow): • Serial Management Interface • MAC Data Interface • Clock Interface • LED Interface • Reset • Strap Options • 10/100 Mb/s PMD Interface • Special Connect Pins • Power and Ground pins All DP83848Q-Q1 signal pins are I/O cells regardless of the particular use.
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DP83848Q-Q1 www.ti.com 3.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 3.2 www.ti.com Package Pin Assignments PIN NO.
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DP83848Q-Q1 www.ti.com 3.3 SNLS341C – MARCH 2011 – REVISED MARCH 2015 Serial Management Interface SIGNAL NAME TYPE PIN NO. MDC I 25 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. MDIO I/O 24 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 3.5 www.ti.com Clock Interface SIGNAL NAME TYPE PIN NO. X1 I 28 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848Q-Q1 and must be connected to a 25 MHz 0.005% (±50 ppm) clock source. The DP83848Q-Q1 supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only.
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DP83848Q-Q1 www.ti.com 3.8 SNLS341C – MARCH 2011 – REVISED MARCH 2015 Strap Options The DP83848Q-Q1 uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses. A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default strap option.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 3.9 www.ti.com 10 Mb/s and 100 Mb/s PMD Interface SIGNAL NAME TYPE PIN NO. DESCRIPTION TD-, TD+ I/O 14 15 Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling. IIn Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3V bias for operation.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 4 Specifications Absolute Maximum Ratings (1) (2) 4.1 MIN MAX UNIT Supply Voltage (VCC) –0.5 4.2 V DC Input Voltage (VIN) –0.5 VCC + 0.5 V DC Output Voltage (VOUT) –0.5 VCC + 0.5 V Maximum Case Temperature for TA = 105°C 115 °C Maximum Die Temperature (TJ) 150 °C 260 °C 150 °C Lead Temp. (TL) (Soldering, 10 sec.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 4.5 www.ti.com Electrical Characteristics: DC PARAMETER VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOL VOH IOZ PIN TYPES I, I/O I, I/O I, I/O O, Voltage I/O µA IOL = 4 mA 0.
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DP83848Q-Q1 www.ti.com 4.6 SNLS341C – MARCH 2011 – REVISED MARCH 2015 Electrical Characteristics: AC PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT POWER UP TIMING (SEE Figure 4-1) T2.1.1 MDIO is pulled high for 32-bit serial management initialization Post Power Up Stabilization time prior to MDC preamble for register accesses (1) X1 Clock must be stable for a min. of 167ms at power up. T2.1.2 Hardware Configuration Pins are described in the Pin Description section.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Electrical Characteristics: AC (continued) PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT 3 4 5 ns 100 Mb/s tR and tF Mismatch (6) (7) 500 ps 100 Mb/s PMD Output Pair Transmit Jitter 1.4 ns 100BASE-TX TRANSMIT TIMING (tR/F AND JITTER) (SEE Figure 4-8) T2.8.1 100 Mb/s PMD Output Pair tR and tF T2.8.2 100BASE-TX RECEIVE PACKET LATENCY TIMING (SEE Figure 4-9) Carrier Sense ON Delay (8) (9) (10) T2.9.1 T2.9.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Electrical Characteristics: AC (continued) PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT 10-Mb/s JABBER TIMING (SEE Figure 4-18) T2.20.1 Jabber Activation Time T2.20.2 Jabber Deactivation Time 85 ms 500 ms 10BASE-T NORMAL LINK PULSE TIMING (SEE Figure 4-19) T2.21.1 Pulse Width 100 ns T2.21.2 Pulse Period 16 ms AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING (SEE Figure 4-20) T2.22.1 Clock, Data Pulse Width 100 ns T2.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Electrical Characteristics: AC (continued) PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal mode 100 µs From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode 500 µs ISOLATION TIMING (SEE Figure 4-26) T2.28.1 T2.28.2 MHz_OUT TIMING (SEE Figure 4-27) T2.29.1 25 MHz_OUT High/Low Time MII mode RMII mode T2.29.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Figure 4-2. Reset Timing Figure 4-3. MII Serial Management Timing Figure 4-4.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Figure 4-5. 100 Mb/s MII Receive Timing Figure 4-6. 100BASE-TX MII Transmit Packet Latency Timing Figure 4-7.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Figure 4-8. 100BASE-TX Transmit Timing (tR/F and Jitter) Figure 4-9. 100BASE-TX Receive Packet Latency Timing Figure 4-10. 100BASE-TX Receive Packet Deassertion Timing Figure 4-11.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Figure 4-12. 10-Mb/s MII Receive Timing TX_CLK TX_EN TXD T2.15.2 PMD Output Pair T2.15.1 Figure 4-13. 10BASE-T Transmit Timing (Start of Packet) Figure 4-14. 10BASE-T Transmit Timing (End of Packet) 1st SFD Bit Decoded 1 0 1 0 1 0 1 0 1 0 1 1 TPRDr T2.17.1 CRS RX_CLK T2.17.2 RX_DV T2.17.3 RXD[3:0] 0000 Preamble SFD Data Figure 4-15.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Figure 4-16. 10BASE-T Receive Timing (End of Packet) Figure 4-17. 10-Mb/s Heartbeat Timing Figure 4-18. 10-Mb/s Jabber Timing Figure 4-19. 10BASE-T Normal Link Pulse Timing Figure 4-20.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Figure 4-21. 100BASE-TX Signal Detect Timing Figure 4-22.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Figure 4-23. 10-Mb/s Internal Loopback Timing Figure 4-24. RMII Transmit Timing Figure 4-25.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Figure 4-26. Isolation Timing Figure 4-27. 25 MHz_OUT Timing Figure 4-28.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 5 Detailed Description 5.1 Overview The device is 10/100 Mbps Ethernet transceiver with an extended temperature range of –40°C to 105°C. The ability to perform over extreme temperatures makes this device ideal for demanding environments like Automotive, Transportation and Industrial Applications. The device is AEC-Q100 Grade 2 certified. Its 3.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 5.3 www.ti.com Feature Description 5.3.1 Auto-Negotiation The Auto-Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. Fast Link Pulse (FLP) Bursts provide the signalling used to communicate Auto-Negotiation abilities between two devices at each end of a link segment.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 The BMSR also provides status on: • Whether or not Auto-Negotiation is complete • Whether or not the Link Partner is advertising that a remote fault has occurred • Whether or not valid link has been established • Support for Management Frame Preamble suppression The Auto-Negotiation Advertisement Register (ANAR) indicates the Auto-Negotiation abilities to be advertised by the DP83848Q-Q1 .
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 5.3.1.6 www.ti.com Auto-Negotiation Complete Time Parallel detection and Auto-Negotiation take approximately 2-3 seconds to complete. In addition, AutoNegotiation with next page should take approximately 2-3 seconds to complete, depending on the number of next pages sent. Refer to Clause 28 of the IEEE 802.3u standard for a full description of the individual timers related to Auto-Negotiation. 5.3.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Specifically, when the LED output is used to drive the LED directly, the active state of the output driver is dependent on the logic level sampled by the AN0 input upon power-up/reset. For example, if the AN0 input is resistively pulled low then the output will be configured as an active high driver. Conversely, if the AN0 input is resistively pulled high, then the output will be configured as an active low driver.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com For transmit VOD testing, the Packet BIST Continuous Mode can be used to allow continuous data transmission, setting BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh). The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 (0x1Bh), bits [15:8]. 5.3.
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DP83848Q-Q1 www.ti.com 5.4.1.2 SNLS341C – MARCH 2011 – REVISED MARCH 2015 Collision Detect For Half Duplex, a 10BASE-T or 100BASE-TX collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII. If the DP83848Q-Q1 is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the FIFO. Underrun and Overrun conditions can be reported in the RMII and Bypass Register (RBR). Table 53 indicates how to program the elasticity buffer fifo (in 4-bit increments) based on expected max packet size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end Transmitter clock) have the same accuracy. Table 5-3.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the first bit of Turnaround. The addressed DP83848Q-Q1 drives the MDIO with a zero for the second bit of turnaround and follows this with the required data.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 5.4.4 www.ti.com PHY Address The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin are shown below. Table 5-5. PHY Address Mapping Pin No. PHYAD Function 42 PHYAD0 RXD Function COL 43 PHYAD1 RXD_0 44 PHYAD2 RXD_1 45 PHYAD3 RXD_2 46 PHYAD4 RXD_3 The DP83848Q-Q1 can be set to respond to any of 32 possible PHY addresses via strap pins.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 The DP83848Q-Q1 can Auto-Negotiate or parallel detect to a specific technology depending on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the DP83848Q-Q1 is in Isolate mode. 5.4.5 Half Duplex vs. Full Duplex The DP83848Q-Q1 supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 5.5 www.ti.com Programming 5.5.1 Architecture This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in the following: • 100BASE-TX Transmitter • 100BASE-TX Receiver • 10BASE-T Transceiver Module 5.5.1.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Table 5-6.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com 5.5.1.1.2 Scrambler The scrambler is required to control the radiated emissions at the media connector and on the twisted-pair cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 5.5.1.2.1 Analog Front End In addition to the Digital Equalization and Gain Control, the DP83848Q-Q1 includes Analog Equalization and Gain Control in the Analog Front End. The Analog Equalization reduces the amount of Digital Equalization required in the DSP. 5.5.1.2.2 Digital Signal Processor The Digital Signal Processor includes Adaptive Equalization with Gain Control and Base Line Wander Compensation. Figure 5-6.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com The DP83848Q-Q1 uses an extremely robust equalization scheme referred as ‘Digital Adaptive Equalization.’ The Digital Equalizer removes ISI (inter symbol interference) from the receive data stream by continuously adapting to provide a filter with the inverse frequency response of the channel. Equalization is combined with an adaptive gain control stage.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 The digital oscilloscope plot provided in Figure 5-9 illustrates the severity of the BLW event that can theoretically be generated during 100BASE-TX packet transmission. This event consists of approximately 800 mV of DC offset for a period of 120 ms. Left uncompensated, events such as this can cause packet loss. 5.5.1.2.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com 5.5.1.2.9 4B/5B Decoder The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble pair (0101 0101).
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally the signal must again exceed the original squelch level within 150 ns to ensure that the input waveform will not be rejected.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com 5.5.1.3.4 Carrier Sense Carrier Sense (CRS) may be asserted due to receive activity once valid data is detected via the squelch function. For 10 Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception. For 10 Mb/s Full Duplex operation, CRS is asserted only during receive activity. CRS is deasserted following an end of packet. 5.5.1.3.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 5.5.1.3.10 Receiver The decoder detects the end of a frame when no additional mid-bit transitions are detected. Within one and a half bit times after the last bit, carrier sense is de-asserted. Receive clock stays active for five more bit times after CRS goes low, to ensure the receive timings of the controller. 5.6 Memory Table 5-7.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Table 5-8.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Table 5-8.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 5.6.1 www.ti.com Register Definition In • • • • • • • • • 5.6.1.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Table 5-9. Basic Mode Control Register (BMCR), address 0x00h (continued) BIT BIT NAME DEFAULT 9 RESTART AUTO-NEGOTIATION 0, RW/SC DUPLEX MODE Strap, RW DESCRIPTION Restart Auto-Negotiation: 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If AutoNegotiation is disabled (bit 12 = 0), this bit is ignored.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Table 5-10. Basic Mode Status Register (BMSR), address 0x01h (continued) BIT BIT NAME DEFAULT 2 LINK STATUS 0, RO/LL DESCRIPTION Link Status: 1 = Valid link established (for either 10 or 100 Mb/s operation). 0 = Link not established. The criteria for link validity is implementation specific. The occurrence of a link failure condition will causes the Link Status bit to clear.
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DP83848Q-Q1 www.ti.com 5.6.1.5 SNLS341C – MARCH 2011 – REVISED MARCH 2015 Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation. Table 5-13. Negotiation Advertisement Register (ANAR), address 0x04h BIT BIT NAME DEFAULT 15 NP 0, RW DESCRIPTION Next Page Indication: 0 = Next Page Transfer not desired. 1 = Next Page Transfer desired.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 5.6.1.6 www.ti.com Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 5-14.
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DP83848Q-Q1 www.ti.com 5.6.1.7 SNLS341C – MARCH 2011 – REVISED MARCH 2015 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 5-15. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05h BIT BIT NAME DEFAULT 15 NP 0, RO DESCRIPTION Next Page Indication: 1 = Link Partner desires Next Page Transfer. 0 = Link Partner does not desire Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 5.6.1.9 www.ti.com Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during AutoNegotiation. Table 5-17. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07h BIT BIT NAME DEFAULT 15 NP 0, RW DESCRIPTION Next Page Indication: 0 = No other Next Page Transfer desired. 1 = Another Next Page desired.
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DP83848Q-Q1 www.ti.com 5.6.2 SNLS341C – MARCH 2011 – REVISED MARCH 2015 Extended Registers 5.6.2.1 PHY Status Register (PHYSTS) This register provides a single location within the register set for quick access to commonly accessed information. Table 5-18. PHY Status Register (PHYSTS), address 10h BIT BIT NAME DEFAULT DESCRIPTION 15 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Table 5-18. PHY Status Register (PHYSTS), address 10h (continued) BIT BIT NAME DEFAULT 5 JABBER DETECT 0, RO DESCRIPTION Jabber Detect: This bit only has meaning in 10 Mb/s mode. This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not cleared upon a read of the PHYSTS register. 1 = Jabber condition detected. 0 = No Jabber.
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DP83848Q-Q1 www.ti.com 5.6.2.3 SNLS341C – MARCH 2011 – REVISED MARCH 2015 Receiver Error Counter Register (RECR) This counter provides information required to implement the “Symbol Error During Carrier” attribute within the PHY managed object class of Clause 30 of the IEEE 802.3u specification. Table 5-20. Receiver Error Counter Register (RECR), address 0x15h BIT BIT NAME DEFAULT 15:8 RESERVED 0, RO 7:0 RXERCNT[7:0] 0, RO/COR DESCRIPTION RESERVED: Writes ignored, read as 0.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 5.6.2.5 www.ti.com RMII and Bypass Register (RBR) This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed. Table 5-22. RMII and Bypass Register (RBR), addresses 0x17h BIT BIT NAME DEFAULT 15:6 RESERVED 0, RO 5 RMII_MODE Strap, RW DESCRIPTION RESERVED: Writes ignored, read as 0. Reduced MII Mode: 0 = Standard MII Mode. 1 = Reduced MII Mode.
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DP83848Q-Q1 www.ti.com 5.6.2.7 SNLS341C – MARCH 2011 – REVISED MARCH 2015 PHY Control Register (PHYCR) This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address. It also provides Pause Negotiation status. Table 5-24. PHY Control Register (PHYCR), address 0x19h BIT BIT NAME DEFAULT 15 MDIX_EN Strap, RW DESCRIPTION Auto-MDIX Enable: 1 = Enable Auto-neg Auto-MDIX capability. 0 = Disable Auto-neg Auto-MDIX capability.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Table 5-24. PHY Control Register (PHYCR), address 0x19h (continued) BIT BIT NAME DEFAULT 5 LED_CFG Strap, RW DESCRIPTION LED Configuration LED_CFG Mode Description 1 Mode 1 0 Mode 2 In Mode 1, LED is configured as follows: LED_LINK = ON for Good Link, OFF for No Link In Mode 2, LED is configured as follows: LED_LINK = ON for good Link, BLINK for Activity 4:0 PHYADDR[4:0] 5.6.2.8 Strap, RW PHY Address: PHY address for port.
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DP83848Q-Q1 www.ti.com 5.6.2.9 SNLS341C – MARCH 2011 – REVISED MARCH 2015 CD Test and BIST Extensions Register (CDCTRL1) This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended control and status for the packet BIST function. Table 5-26. CD Test and BIST Extensions Register (CDCTRL1), address 0x1Bh BIT BIT NAME DEFAULT 15:8 BIST_ERROR_COUNT 0, RO DESCRIPTION BIST ERROR Counter: Counts number of errored data nibbles during Packet BIST.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com 5.6.2.10 Energy Detect Control (EDCR) This register provides control and status for the Energy Detect function. Table 5-27. Energy Detect Control (EDCR), address 0x1Dh BIT BIT NAME DEFAULT 15 ED_EN 0, RW DESCRIPTION Energy Detect Enable: Allow Energy Detect Mode. When Energy Detect is enabled and Auto-Negotiation is disabled via the BMCR register, Auto-MDIX should be disabled via the PHYCR register.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 6 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 6.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Figure 6-2. 10/100-Mb/s Twisted-Pair Interface 6.2.1.2 Clock IN (X1) Requirements The DP83848Q-Q1 supports an external CMOS level oscillator source or a crystal resonator device. Oscillator If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating. Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 6-1 and Table 6-2.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Table 6-1.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 6.2.1.4 www.ti.com Magnetics The magnetics have a large impact on the PHY performance as well. While several components are listed below, others may be compatible following the requirements listed in Table 6-4. It is recommended that the magnetics include both an isolation transformer and an integrated common mode choke to reduce EMI. When doing the layout, do not run signals under the magnetics. This could cause unwanted noise crosstalk.
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DP83848Q-Q1 www.ti.com 6.2.2.4 SNLS341C – MARCH 2011 – REVISED MARCH 2015 Calculating Impedance Equation 2 through Equation 5 can be used to calculate the differential impedance of the board. For microstrip traces, a solid ground plane is needed under the signal traces. The ground plane helps keep the EMI localized and the trace impedance continuous. Because stripline traces are typically sandwiched between the ground/supply planes, they have the advantage of lower EMI radiation and less noise coupling.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Figure 6-7. Microstrip Impedance - Differential Stripline Impedance - Differential: Zdiff = 2Zo Sö æ ç -2.9 ÷ Hø è (1 - 0.347(e ) (5) Figure 6-8. Stripline Impedance - Differential 6.2.3 Application Curve Figure 6-9. Sample 100-Mb/s Waveform (MLT-3) 68 Figure 6-10.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 7 Power Supply Recommendations The device Vdd supply pins should be bypassed with low impedance 0.1-μF surface mount capacitors. To reduce EMI, the capacitors should be places as close as possible to the component Vdd supply pins, preferably between the supply pins and the vias connecting to the power plane.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com 8 Layout 8.1 8.1.1 Layout Guidelines PCB Layout Considerations Place the 49.9-Ω,1% resistors, and 0.1-μF decoupling capacitor, near the PHYTER TD± and RD± pins and via directly to the Vdd plane. Stubs should be avoided on all signal traces, especially the differential signal pairs. See Figure 8-1. Within the pairs (for example, TD+ and TD–) the trace lengths should be run parallel to each other and matched in length.
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DP83848Q-Q1 www.ti.com SNLS341C – MARCH 2011 – REVISED MARCH 2015 Figure 8-3. PCB Stripline Layer Stacking Within a PCB it may be desirable to run traces using different methods, microstrip vs. stripline, depending on the location of the signal on the PCB. For example, it may be desirable to change layer stacking where an isolated chassis ground plane is used. Figure 8-4 illustrates alternative PCB stacking options.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com Figure 8-4.
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DP83848Q-Q1 www.ti.com 8.2 SNLS341C – MARCH 2011 – REVISED MARCH 2015 Layout Example Figure 8-5.
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DP83848Q-Q1 SNLS341C – MARCH 2011 – REVISED MARCH 2015 www.ti.com 9 Device and Documentation Support 9.1 Documentation Support 9.1.1 Related Documentation • • 9.2 AN-1405 DP83848 Single 10/100 Mb/s Ethernet Transceiver Reduced Media Independent Interface™ (RMII™) Mode, SNLA076 PHYTER 100 Base-TX Reference Clock Jitter Tolerance, SNLA091 Trademarks PHYTER is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 9.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 8-Sep-2014 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Sep-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DP83848QSQ/NOPB WQFN RTA 40 DP83848QSQE/NOPB WQFN RTA DP83848QSQX/NOPB WQFN RTA SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 40 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Sep-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DP83848QSQ/NOPB WQFN RTA 40 1000 367.0 367.0 38.0 DP83848QSQE/NOPB WQFN RTA 40 250 213.0 191.0 55.0 DP83848QSQX/NOPB WQFN RTA 40 2500 367.0 367.0 38.
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PACKAGE OUTLINE RTA0040A WQFN - 0.8 mm max height SCALE 2.200 PLASTIC QUAD FLATPACK - NO LEAD 6.1 5.9 A B PIN 1 INDEX AREA 6.1 5.9 0.5 0.3 0.3 0.2 DETAIL OPTIONAL TERMINAL TYPICAL 0.8 MAX C SEATING PLANE 0.08 0.05 0.00 4.6 0.1 36X 0.5 10 (0.1) TYP EXPOSED THERMAL PAD 20 11 21 4X 4.5 SEE TERMINAL DETAIL 1 PIN 1 ID (OPTIONAL) 30 40 31 40X 0.5 0.3 40X 0.3 0.2 0.1 0.05 C A B 4214989/A 12/2014 NOTES: 1. All linear dimensions are in millimeters.
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EXAMPLE BOARD LAYOUT RTA0040A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 4.6) SYMM 40X (0.25) 31 40 40X (0.6) 1 30 36X (0.5) (0.74) TYP SYMM (5.8) (1.48) TYP ( 0.2) TYP VIA 10 21 (R0.05) TYP 11 20 (0.74) TYP (1.48) TYP (5.8) LAND PATTERN EXAMPLE SCALE:12X 0.07 MIN ALL AROUND 0.
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EXAMPLE STENCIL DESIGN RTA0040A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD (1.48) TYP 9X ( 1.28) 31 40 40X (0.6) 1 30 40X (0.25) 36X (0.5) (1.48) TYP SYMM (5.8) METAL TYP 10 21 (R0.05) TYP 20 11 SYMM (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 70% PRINTED SOLDER COVERAGE BY AREA SCALE:15X 4214989/A 12/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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