User manual

UM0036 In-circuit debugging
Doc ID 7705 Rev 11 235/385
TRAP instruction limitation (ICC only)
The TRAP interrupt vector is reserved for the ICC monitor during debugging and TRAP
instructions must not be used in the application.
Peripheral limitation (ICC only)
On some old devices, when the execution of your application is stopped from STVD while in-
circuit debugging, the peripherals (notably, the timers) are not frozen.
Reset limitation
The reset is not real-time.
In ICC the microcontroller executes the ICC monitor after a reset until the host debugger
sends a “continue” command.
In SWIM the microcontroller remains stalled until the host debugger sends a “continue”
command.
External reset limitation
Hardware on the application board must not generate external resets when the application
is stopped. The effect is different depending on the debugging protocol.
When debugging over ICC, an external reset results in the loss of synchronization between
STVD and the application. If this occurs, select Debug>Stop Debugging and then
Debug>Start Debugging to restart your in-circuit debugging session.
When debugging over SWIM, an external reset may cause a SWIM communication error
(timeout). Communication is re-established when the reset is released.
Address 0x80-0x81 overwrite on reset (ICC only)
When starting the user application (Debug>Run) after a chip reset, the ICC monitor
automatically overwrites any values stored at 0x80-0x81 with values corresponding to the
microcontroller's die identifier.
HDFlash devices Flash memory limitation (ICC only)
On devices with HDFlash memory, the ICC Monitor must be copied to a sector of Flash
memory because the system memory does not contain the advanced ICC monitor that is
required for in-circuit debugging. This zone of Flash memory will not be available for your
application. If your application attempts to write to this memory zone you will receive an
error message indicating that the application has tried to write to a reserved memory
zone.The affected devices and memory zone are listed in Ta bl e 72 .
Table 72. Flash memory limitation on HDFlash devices
Affected microcontrollers Address range of reserved memory zone
ST7FLCD1 FF00 - FFDF
ST7FMC2 FF00 - FFDF
ST72F325 FF00 - FFDF