Technical data

12
Chapter 1: DVP Specifications
must not be exceeded; swap-rates must match across channels) apply to DVP as they do
to the analog video channels.
Genlocking DG4 to External Sources
The equipment connected to the DVP interface is expected to be slaved to the video
timing of the DG4 board via the DVP signals FRAME_{H,L}, VSYNC_{H,L},
CSYNC_{H,L}, and CBLANK_{H,L}. Operating the receiver in slave mode results in the
absolute minimum video data latency.
In certain applications, the DG4 video output can be slaved to the external equipment.
This should be done using the DG4 external frame-locking facility. (See DG4
documentation for more information.) The horizontal phase adjustment of DG4 genlock
circuits can be used to adjust for delays in cabling and equipment. However, the user is
cautioned against expecting pixel- or sub-pixel accuracy. In most cases, such accuracy is
not necessary. The receiving equipment may require FIFO memories to receive video
data in order to operate reliably in this mode. These FIFO memories may increase the
latency of the DVP video channel depending on their depth. Proper consideration of
these important design issues in the early stages of the receiver design will avoid
unforeseen problems later on.