Technical data

8
Chapter 1: DVP Specifications
Suggested Receiver Design
Over most of the DVP’s operating range, clock skew is an important consideration in the
transmission of pixel clock to the video option board and distributing it to the video
option board. Because of its wide operating limits, phase-locked-loop techniques are
unsuitable for receiving the clocks on the DVP interface. Figure 1-4 shows the circuit
recommended by Silicon Graphics for receiving and regenerating a full-speed pixel
clock, the method of distributing it, and the recommended circuits for receiving DVP
video data. The recommended data receiver is a Motorola MC100E452. The
recommended clock receiver is a Synergy Semiconductor SY100EL16A.