Technical data

6
Chapter 1: DVP Specifications
• VOC_SWAP can also be programmed to be continuously HI or LOW.
For more information, contact Silicon Graphics technical support or your local service
provider.
Other Signals (HMUX_SEL{1,0}_{H,L})
These signals are reserved for future development of the DVP interface. The current
implementation always asserts these two signal pairs as LOW.
Receiver Power Indicator (PWR_GOOD)
The DVP interface uses differential, 5-volt positive-ECL (5V-PECL) signalling, which
provides speed and the ability to correctly terminate transmission lines. However,
because of the circuit configuration of ECL driver circuits, damage can result if the
drivers attempt to drive powered-down receivers. For this reason, the DVP interface
expects the receiving equipment to send a voltage equal to the power supply voltage of
the 5V-PECL clock and data receiver circuits. (The voltage should be current-limited for
safety considerations.) Under normal operating conditions, this pin should provide the
DVP board with 0.1 mA of 4.6 V to 5.8 V. If PWR_GOOD is not in this range (with respect
to ground on the DVP board), the DVP PECL circuitry will be powered down to avoid
damage.
I
2
C signals (I2C_DATA, I2C_CLOCK)
These signals support the VESA DDC standard for communicating with video
peripherals (monitors, projectors, LCD panels, etc.) using the Phillips I
2
C standard. These
signals are not 5V_PECL signals. I2C_DATA is open-collector, 5V-TTL. I2C_CLOCK is
5V-TTL. The DVP board implements these signals using the Phillips PFC8584 I
2
C
Controller. Phillips’ application literature has more information about I
2
C and this
controller chip. Unless you are designing equipment that supports the VESA DDC
standard, disregard these signals and make no connection to them. (For more
information, contact Silicon Graphics technical support or your local service provider.)