Datasheet

VCNL36687S
www.vishay.com
Vishay Semiconductors
Rev. 1.2, 21-Sep-2018
5
Document Number: 84907
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PARAMETER TIMING INFORMATION
Fig. 2 - I
2
C Bus Timing for Sending Word Command Format
Fig. 3 - I
2
C Bus Timing for Receiving Word Command Format
W
SA6
SA5 SA4 SA3 SA2
SA1
SA7
I
2
C bus slave address byte
SA6 SA5 SA4 SA3 SA2
SA0
SA7
Command code
SA1
SA7
SA6 SA5
SA4 SA3
SA2 SA1
SA0
SA7
SA6 SA5
SA4 SA3 SA2 SA1
SA0
Data byte low Data byte high
I
2
C BUS
CLOCK
(SCLK)
I
2
C BUS
DATA
(SDAT)
I
2
C BUS
CLOCK
(SCLK)
I
2
C BUS
DATA
(SDAT)
Start by
master
ACK by
VCNL36687S
ACK by
VCNL36687S
ACK by
VCNL36687S
ACK by
VCNL36687S
Stop by
master
W
I
2
C bus slave address byte
Command code
SA6 SA5 SA4 SA3 SA2
SA1SA7
SA6 SA5 SA4 SA3 SA2 SA0SA7 SA1
SA7
SA6 SA5 SA4 SA3 SA2 SA1
SA0
Data byte high
R
I
2
C bus slave address byte
Data byte low
SA6 SA5 SA4 SA3 SA2
SA6 SA5 SA4 SA3 SA2
SA0
SA7 SA1
SA1
SA7
I
2
C BUS
CLOCK
(SCLK)
I
2
C BUS
DATA
(SDAT)
I
2
C BUS
CLOCK
(SCLK)
I
2
C BUS
DATA
(SDAT)
I
2
C BUS
CLOCK
(SCLK)
I
2
C BUS
DATA
(SDAT)
Start by
master
ACK by
VCNL36687S
ACK by
VCNL36687S
ACK by
VCNL36687S
ACK by
master
Start by
master
Stop by
master
NACK by
master