Datasheet

AN816
Vishay Siliconix
www.vishay.com
2
Document Number: 71405
12-Dec-03
FIGURE 3.
Front of Board SC70-6 Back of Board SC70-6
D1
G2
S2
S1
G1
D2
SC70−6 DUAL
vishay.com
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(the Package Performance)
Thermal performance for the dual SC-70 6-pin package is
measured as junction-to-foot thermal resistance, in which the
“foot” is the drain lead of the device as it connects with the
body. The junction-to-foot thermal resistance for this device is
typically 80_C/W, with a maximum thermal resistance of
approximately 100_C/W. This data compares favorably with
another compact, dual-channel package – the dual TSOP-6 –
which features a typical thermal resistance of 75_C/W and a
maximum of 90_C/W.
Power Dissipation
The typical Rθ
JA
for the dual-channel 6-pin SC-70 with a
copper leadframe is 224_ C/W steady-state, compared to
413_C/W for the Alloy 42 version. All figures are based on the
1-inch
2
FR4 test board. The following example shows how the
thermal resistance impacts power dissipation for the dual 6-pin
SC-70 package at varying ambient temperatures.
Alloy 42 Leadframe
ALLOY 42 LEADFRAME
Room Ambient 25 _C Elevated Ambient 60 _C
P
D
+
T
J(max)
* T
A
Rq
JA
P
D
+
150
o
C * 25
o
C
413
o
CńW
P
D
+ 303 mW
P
D
+
T
J(max)
* T
A
Rq
JA
P
D
+
150
o
C * 60
o
C
413
o
CńW
P
D
+ 218 mW
COOPER LEADFRAME
Room Ambient 25 _C Elevated Ambient 60 _C
P
D
+
T
J(max)
* T
A
Rq
JA
P
D
+
150
o
C * 25
o
C
224
o
CńW
P
D
+ 558 mW
P
D
+
T
J(max)
* T
A
Rq
JA
P
D
+
150
o
C * 60
o
C
224
o
CńW
P
D
+ 402 mW
Although they are intended for low-power applications,
devices in the 6-pin SC-70 dual-channel configuration will
handle power dissipation in excess of 0.5 W.
TESTING
To further aid the comparison of copper and Alloy 42
leadframes, Figures 4 and 5 illustrate the dual-channel 6-pin
SC-70 thermal performance on two different board sizes and
pad patterns. The measured steady-state values of Rθ
JA
for
the dual 6-pin SC-70 with varying leadframes are as follows:
LITTLE FOOT 6-PIN SC-70
Alloy 42 Copper
1) Minimum recommended pad pattern on
the EVB board (see Figure 3).
518_C/W 344_C/W
2) Industry standard 1-inch
2
PCB with
maximum copper both sides.
413_C/W 224_C/W
The results indicate that designers can reduce thermal
resistance (θJA) by 34% simply by using the copper leadframe
device as opposed to the Alloy 42 version. In this example, a
174_C/W reduction was achieved without an increase in board
area. If an increase in board size is feasible, a further 120_C/W
reduction can be obtained by utilizing a 1-inch
2
. PCB area.
The Dual copper leadframe versions have the following suffix:
Dual: Si19xxEDH
Compl.: Si15xxEDH