Datasheet

SiHH068N60E
www.vishay.com
Vishay Siliconix
S18-0934-Rev. B, 17-Sep-2018
6
Document Number: 92121
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Fig. 18 - Basic Gate Charge Waveform
Fig. 19 - Gate Charge Test Circuit
Fig. 20 - For N-Channel

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Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?92121
.
Q
gs
Q
gd
Q
g
V
G
Charge
10 V
D.U.T.
3 mA
V
GS
V
DS
I
G
I
D
0.3 μF
0.2 μF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
P.W.
Period
di/dt
Diode recovery
dv/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
V
GS
= 10 V
a
V
DD
I
SD
Driver gate drive
D.U.T. I
SD
waveform
D.U.T. V
DS
waveform
Inductor current
D =
P.W.
Period
+
-
+
+
+
-
-
-
Note
a. V
GS
= 5 V for logic level devices
Peak Diode Recovery dv/dt Test Circuit
V
DD
• dv/dt controlled by R
g
• Driver same type as D.U.T.
• I
SD
controlled by duty factor “D”
• D.U.T. - device under test
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
R
g
2
1
2
1
3
4
4
3