Datasheet

ManualsBrandsVISHAY ManualsFETsIRLD120PBF, MOSFET DIP-4

Document Number: 91310 www.vishay.com

S10-2465-Rev. C, 08-Nov-10 1

Power MOSFET

IRLD120, SiHLD120

Vishay Siliconix

FEATURES

• Dynamic dV/dt Rating

• Repetitive Avalanche Rated

• For Automatic Insertion

• End Stackable

• Logic-Level Gate Drive

•R

DS(on)

Specified at V

= 4 V and 5 V

• 175 °C Operating Temperature

• Compliant to RoHS Directive 2002/95/EC

DESCRIPTION

Third generation Power MOSFETs from Vishay provide the

designer with the best combination of fast switching,

ruggedized device design, low on-resistance and

cost-effectiveness.

The 4 pin DIP package is a low cost machine-insertable case

style which can be stacked in multiple combinations on

standard 0.1" pin centers. The dual drain serves as a thermal

link to the mounting surface for power dissipation levels up to

1 W.

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. V

= 25 V, starting T

= 25 °C, L = 153 mH, R

= 25 , I

= 2.6 A (see fig. 12).

c. I

 9.2 A, dI/dt  110 A/µs, V

 V

, T

 175 °C.

d. 1.6 mm from case.

PRODUCT SUMMARY

(V) 100

DS(on)

()V

= 5.0 V 0.27

(Max.) (nC) 12

(nC) 3.0

(nC) 7.1

Configuration Single

N-Channel MOSFET

HVMDIP

Available

RoHS*

COMPLIANT

ORDERING INFORMATION

Package HVMDIP

Lead (Pb)-free

IRLD120PbF

SiHLD120-E3

SnPb

IRLD120

SiHLD120

ABSOLUTE MAXIMUM RATINGS (T

= 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

100

Gate-Source Voltage V

± 10

Continuous Drain Current V

at 5.0 V

= 25 °C

1.3

= 100 °C 0.94

Pulsed Drain Current

Linear Derating Factor 0.0083 W/°C

Single Pulse Avalanche Energy

690 mJ

Avalanche Current

1.3 A

Repetitive Avalanche Energy

0.13 mJ

Maximum Power Dissipation T

= 25 °C P

1.3 W

Peak Diode Recovery dV/dt

dV/dt 5.5 V/ns

Operating Junction and Storage Temperature Range T

, T

stg

- 55 to + 175

°C

Soldering Recommendations (Peak Temperature) for 10 s 300

* Pb containing terminations are not RoHS compliant, exemptions may apply

Summary of content (9 pages)

PAGE 1
IRLD120, SiHLD120 Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Dynamic dV/dt Rating 100 RDS(on) () VGS = 5.0 V Qg (Max.) (nC) 12 Qgs (nC) 3.0 Qgd (nC) 7.1 Configuration Available • Repetitive Avalanche Rated 0.
PAGE 2
IRLD120, SiHLD120 Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient SYMBOL TYP. MAX. UNIT RthJA - 120 °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX.
PAGE 3
IRLD120, SiHLD120 Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 20 µs PULSE WIDTH TA = 25 °C Fig. 1 - Typical Output Characteristics, TA = 25 °C Fig. 3 - Typical Transfer Characteristics 20 µs PULSE WIDTH TA = 175 °C Fig. 2 - Typical Output Characteristics, TA = 175 °C Document Number: 91310 S10-2465-Rev. C, 08-Nov-10 Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.
PAGE 4
IRLD120, SiHLD120 Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage TA = 25 °C TJ = 175 °C SINGLE PULSE Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Fig. 8 - Maximum Safe Operating Area Document Number: 91310 S10-2465-Rev.
PAGE 5
IRLD120, SiHLD120 Vishay Siliconix VDS VGS RD D.U.T. ID, Drain Current (A) Rg + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS TA, Ambient Temperature (°C) td(on) td(off) tf Fig. 10b - Switching Time Waveforms Thermal Response (ZthJA) Fig. 9 - Maximum Drain Current vs. Ambient Temperature tr t1, Rectangular Pulse Duration (s) Fig.
PAGE 6
IRLD120, SiHLD120 Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T Rg + - I AS V DD VDS 5V 0.01 W tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig.
PAGE 7
IRLD120, SiHLD120 Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T.
PAGE 8
Package Information Vishay Siliconix HVM DIP (High voltage) 0.248 [6.29] 0.240 [6.10] 0.043 [1.09] 0.035 [0.89] 0.197 [5.00] 0.189 [4.80] 0.133 [3.37] 0.125 [3.18] 0.180 [4.57] 0.160 [4.06] 0.094 [2.38] 0.086 [2.18] A L 0.160 [4.06] 0.140 [3.56] 0° to 15° 2x 0.017 [0.43] 0.013 [0.33] 0.045 [1.14] 2 x 0.035 [0.89] E min. 0.024 [0.60] 4x 0.020 [0.51] 0.100 [2.54] typ. E max. INCHES MILLIMETERS DIM. MIN. MAX. MIN. A 0.310 0.330 7.87 MAX. 8.38 E 0.300 0.425 7.62 10.79 L 0.270 0.
PAGE 9
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