Datasheet

ManualsBrandsVISHAY ManualsFETsIRFI840GLCPBF, MOSFET

Document Number: 91160 www.vishay.com

S-81292-Rev. A, 16-Jun-08 1

Power MOSFET

IRFI840GLC, SiHFI840GLC

Vishay Siliconix

FEATURES

• Ultra Low Gate Charge

• Reduced Gate Drive Requirement

• Enhanced 30 V V

Rating

• Isolated Package

• High Voltage Isolation = 2.5 kV

RMS

(t = 60 s; f = 60 Hz)

• Sink to Lead Creepage Distance = 4.8 mm

• Repetitve Avalanche Rated

• Lead (Pb)-free Available

DESCRIPTION

This new series of low charge Power MOSFETs achieve

significantly lower gate charge over conventional MOSFETs.

Utilizing advanced Power MOSFET technology, the device

improvements allow for reduced gate drive requirements,

faster switching speeds and increased total system savings.

These device improvements combined with the proven

ruggedness and reliability that are characteristic of

MOSFETs offer the designer a new standard in power

transistors for switching applications.

The TO-220 FULLPAK eliminates the need for additional

insulating hardware. The molding compound used provides

a high isolation capability and low thermal resistance

between the tab and external heatsink.

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. V

= 50 V, starting T

= 25 °C, L = 26 mH, R

= 25 Ω, I

= 4.5 A (see fig. 12).

c. I

≤ 8.0 A, dI/dt ≤ 100 A/µs, V

≤ V

, T

≤ 150 °C.

d. 1.6 mm from case.

PRODUCT SUMMARY

(V) 500

DS(on)

(Ω)V

= 10 V 0.85

(Max.) (nC) 39

(nC) 10

(nC) 19

Configuration Single

N-Channel MOSFET

TO-220 FULLPAK

Available

RoHS*

COMPLIANT

ORDERING INFORMATION

Package TO-220 FULLPAK

Lead (Pb)-free

IRFI840GLCPbF

SiHFI840GLC-E3

SnPb

IRFI840GLC

SiHFI840GLC

ABSOLUTE MAXIMUM RATINGS T

= 25 °C, unless otherwise noted

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

500

Gate-Source Voltage V

± 30

Continuous Drain Current V

at 10 V

= 25 °C

4.5

= 100 °C 2.9

Pulsed Drain Current

Linear Derating Factor 0.32 W/°C

Single Pulse Avalanche Energy

300 mJ

Repetitive Avalanche Current

4.5 A

Repetitive Avalanche Energy

4.0 mJ

Maximum Power Dissipation T

= 25 °C P

40 W

Peak Diode Recovery dV/dt

dV/dt 3.5 V/ns

Operating Junction and Storage Temperature Range T

, T

stg

- 55 to + 150

°C

Soldering Recommendations (Peak Temperature) for 10 s 300

Mounting Torque 6-32 or M3 screw

10 lbf · in

1.1 N · m

* Pb containing terminations are not RoHS compliant, exemptions may apply

Summary of content (8 pages)

PAGE 1
IRFI840GLC, SiHFI840GLC Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • • 500 RDS(on) (Ω) VGS = 10 V 0.85 Qg (Max.) (nC) 39 Qgs (nC) 10 Qgd (nC) 19 Configuration Single D TO-220 FULLPAK Ultra Low Gate Charge Reduced Gate Drive Requirement Available Enhanced 30 V VGS Rating RoHS* COMPLIANT Isolated Package High Voltage Isolation = 2.5 kVRMS (t = 60 s; f = 60 Hz) Sink to Lead Creepage Distance = 4.
PAGE 2
IRFI840GLC, SiHFI840GLC Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 65 Maximum Junction-to-Case (Drain) RthJC - 3.1 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 µA 500 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.63 - V/°C VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.
PAGE 3
IRFI840GLC, SiHFI840GLC Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 3 - Typical Transfer Characteristics Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91160 S-81292-Rev. A, 16-Jun-08 www.vishay.
PAGE 4
IRFI840GLC, SiHFI840GLC Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area Document Number: 91160 S-81292-Rev.
PAGE 5
IRFI840GLC, SiHFI840GLC Vishay Siliconix RD VDS VGS D.U.T. RG + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case VDS L Vary tp to obtain required IAS VDS tp D.U.T RG + - IAS V DD A 10 V tp 0.01 Ω IAS Fig.
PAGE 6
IRFI840GLC, SiHFI840GLC Vishay Siliconix Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91160 S-81292-Rev.
PAGE 7
IRFI840GLC, SiHFI840GLC Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test Driver gate drive P.W. + Period D= + - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T.
PAGE 8
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