Datasheet

ManualsBrandsVISHAY ManualsFETsIRFD210PBF, MOSFET DIP-4

Document Number: 91129 www.vishay.com

S10-2462-Rev. C, 08-Nov-10 1

Power MOSFET

IRFD210, SiHFD210

Vishay Siliconix

FEATURES

• Dynamic dV/dt Rating

• Repetitive Avalanche Rated

• For Automatic Insertion

•End Stackable

•Fast Switching

• Ease of Paralleling

• Simple Drive Requirements

• Compliant to RoHS Directive 2002/95/EC

DESCRIPTION

Third generation Power MOSFETs from Vishay provide the

designer with the best combination of fast switching,

ruggedized device design, low on-resistance and

cost-effectiveness.

The 4 pin DIP package is a low cost machine-insertable

case style which can be stacked in multiple combinations on

standard 0.1" pin centers. The dual drain serves as a thermal

link to the mounting surface for power dissipation levels up

to 1 W.

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. V

= 50 V, starting T

= 25 °C, L = 82 mH, R

= 25 , I

= 1.2 A (see fig. 12).

c. I

 3.3 A, dI/dt  70 A/μs, V

 V

, T

 150 °C.

d. 1.6 mm from case.

PRODUCT SUMMARY

(V) 200

DS(on)

()V

= 10 V 1.5

(Max.) (nC) 8.2

(nC) 1.8

(nC) 4.5

Configuration Single

N-Channel MOSFET

HVMDIP

Available

RoHS*

COMPLIANT

ORDERING INFORMATION

Package HVMDIP

Lead (Pb)-free

IRFD210PbF

SiHFD210-E3

SnPb

IRFD210

SiHFD210

ABSOLUTE MAXIMUM RATINGS (T

= 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

200

Gate-Source Voltage V

± 20

Continuous Drain Current V

at 10 V

= 25 °C

0.60

= 100 °C 0.38

Pulsed Drain Current

4.8

Linear Derating Factor 0.0083 W/°C

Single Pulse Avalanche Energy

79 mJ

Repetitive Avalanche Current

0.60 A

Repetitive Avalanche Energy

0.10 mJ

Maximum Power Dissipation T

= 25 °C P

1.0 W

Peak Diode Recovery dV/dt

dV/dt 5.0 V/ns

Operating Junction and Storage Temperature Range T

, T

stg

- 55 to + 150

°C

Soldering Recommendations (Peak Temperature) for 10 s 300

* Pb containing terminations are not RoHS compliant, exemptions may apply

Summary of content (9 pages)

PAGE 1
IRFD210, SiHFD210 Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • • 200 RDS(on) () VGS = 10 V 1.5 Qg (Max.) (nC) 8.2 Qgs (nC) 1.8 Qgd (nC) 4.
PAGE 2
IRFD210, SiHFD210 Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient SYMBOL TYP. MAX. UNIT RthJA - 120 °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 μA 200 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.30 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.
PAGE 3
IRFD210, SiHFD210 Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) TA = 25 °C Fig. 1 - Typical Output Characteristics, TA = 25 °C Fig. 3 - Typical Transfer Characteristics TA = 150 °C Fig. 2 - Typical Output Characteristics, TA = 150 °C Document Number: 91129 S10-2462-Rev. C, 08-Nov-10 Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.
PAGE 4
IRFD210, SiHFD210 Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage TA = 25 °C TJ = 150 °C SINGLE PULSE Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Fig. 8 - Maximum Safe Operating Area Document Number: 91129 S10-2462-Rev.
PAGE 5
IRFD210, SiHFD210 Vishay Siliconix RD VDS VGS D.U.T. ID, Drain Current (A) Rg + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % TA, Ambient Temperature (°C) 10 % VGS td(on) td(off) tf Fig. 10b - Switching Time Waveforms Thermal Response (ZthJA) Fig. 9 - Maximum Drain Current vs. Ambient Temperature tr t1, Rectangular Pulse Duration (s) Fig.
PAGE 6
IRFD210, SiHFD210 Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T. Rg + - IAS V DD VDS 10 V 0.01 W tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig.
PAGE 7
IRFD210, SiHFD210 Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T.
PAGE 8
Package Information Vishay Siliconix HVM DIP (High voltage) 0.248 [6.29] 0.240 [6.10] 0.043 [1.09] 0.035 [0.89] 0.197 [5.00] 0.189 [4.80] 0.133 [3.37] 0.125 [3.18] 0.180 [4.57] 0.160 [4.06] 0.094 [2.38] 0.086 [2.18] A L 0.160 [4.06] 0.140 [3.56] 0° to 15° 2x 0.017 [0.43] 0.013 [0.33] 0.045 [1.14] 2 x 0.035 [0.89] E min. 0.024 [0.60] 4x 0.020 [0.51] 0.100 [2.54] typ. E max. INCHES MILLIMETERS DIM. MIN. MAX. MIN. A 0.310 0.330 7.87 MAX. 8.38 E 0.300 0.425 7.62 10.79 L 0.270 0.
PAGE 9
Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.