Service manual
Table Of Contents
- VIZIO L42HDTV10A,GV42L_HDTV Service Manual
- 01-FEATURES
- 02-SPECIFITION
- 03-ON SCREEN DISPLAY
- 04-FACTORY PRESET TIMINGS
- 05-PIN ASSIGNMENT
- 06-MAIN BOARD I/O CONNECTIONS
- 07-THEORY OF CIRCUIT OPERATION
- 08-WAVEFORMS
- 09-TROUBLE SHOOTING
- 10-BLOCK DIAGRAM
- 11-SPARE PATRS LIST
- 12-1COMPLETE PARTS LIST_FOR L42 HDTV10A
- 12-2COMPLETE PARTS LIST_FOR GV42L HDTV
- MAIN BOARD CIRCUIT DIAGRAM_FOR L42 HDTV10A
- MIAN BOARD CIRCUIT DIAGRAM_FOR GV42L HDTV
- MAIN BOARD PCB LAYOUT_FOR L42HDTV10A(LG/AUO)
- MAIN BOARD PCB LAYOUT_FOR GV42L HDTV_LG
- ASSEMBLY EXPLOSION DRAWING_FOR L42HDTV10A_AUO
- ASSEMBLY EXPLOSION DRAWING_FOR L42HDTV10A_LG
- ASSEMBLY EXPLOSION DRAWING_FOR GV42L HDTV_LG
CONFIDENTIAL – DO NOT COPY
Page 7-28
File No. SG-0198
The receiver can also process the video data before it is output as show below figure
5. I
2
c Interface to Display Controller
The Controller I
2
c interface (CSDA, CSCL) on the MT8293 is a slave interface capable of running
up to 400KHZ. This bus is used to configure the MT8293 by reading/writing to the appropriate
registers. The MT8293 is accessible on the local I
2
c bits at two-device address. The logic state of
the CI2CA pin is latched on the rising edge of REST# providing a choice of two pairs of device
address.
Control of local I
2
c address with CI2CA pin
TDA8946 Application
In L32 TV the TDA8946AJ is a dual-channel audio power amplifier with DC gain control. It has an
output power of 2 × 10 W at an 8 Ω load and a 12 V supply.