Service manual
Table Of Contents
- VIZIO L42HDTV10A,GV42L_HDTV Service Manual
- 01-FEATURES
- 02-SPECIFITION
- 03-ON SCREEN DISPLAY
- 04-FACTORY PRESET TIMINGS
- 05-PIN ASSIGNMENT
- 06-MAIN BOARD I/O CONNECTIONS
- 07-THEORY OF CIRCUIT OPERATION
- 08-WAVEFORMS
- 09-TROUBLE SHOOTING
- 10-BLOCK DIAGRAM
- 11-SPARE PATRS LIST
- 12-1COMPLETE PARTS LIST_FOR L42 HDTV10A
- 12-2COMPLETE PARTS LIST_FOR GV42L HDTV
- MAIN BOARD CIRCUIT DIAGRAM_FOR L42 HDTV10A
- MIAN BOARD CIRCUIT DIAGRAM_FOR GV42L HDTV
- MAIN BOARD PCB LAYOUT_FOR L42HDTV10A(LG/AUO)
- MAIN BOARD PCB LAYOUT_FOR GV42L HDTV_LG
- ASSEMBLY EXPLOSION DRAWING_FOR L42HDTV10A_AUO
- ASSEMBLY EXPLOSION DRAWING_FOR L42HDTV10A_LG
- ASSEMBLY EXPLOSION DRAWING_FOR GV42L HDTV_LG
CONFIDENTIAL – DO NOT COPY
Page 7-24
File No. SG-0198
2. DIGITAL AUDIO INTERFACE
1. Slave mode
The audio interfaces operations in either slave mode selectable using the MS control bit. In slave
mode DIN is always an input to the WM8776 and DOUT is always an output. The default is Slave
mode. In slave mode (ms=0) ADCLRC, DACLRC, ADCBCLK, DACBCLK are input to the WM8776
DIN and DACLRC are sampled by the WM8776 on the rising edge of DACBCLK; ADCLRC is
sampled on the rising edge of ADCBCLK. ADC data is output on DOUT and changes on the falling
edge of ADCBCLK. By setting control bit BCLKINV the polarity of ADCBCLK and DACBCLK may
be reversed so that DIN and DACLRC are sample on the falling edge of DACBCLK, ADCLRC is
sampled on the falling edge of ADCBCLK and DOUT changes on the rising of ADCBCLK
Slave mode as shown in the following figure.
2. 2 Wire serial control mode
The wm8776 supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit
address of each register in the wm8776). The wm8776 operates as a slave device only.
2-wire serial interface as shown in the following figure.