Service manual
Table Of Contents
- VIZIO L42HDTV10A,GV42L_HDTV Service Manual
- 01-FEATURES
- 02-SPECIFITION
- 03-ON SCREEN DISPLAY
- 04-FACTORY PRESET TIMINGS
- 05-PIN ASSIGNMENT
- 06-MAIN BOARD I/O CONNECTIONS
- 07-THEORY OF CIRCUIT OPERATION
- 08-WAVEFORMS
- 09-TROUBLE SHOOTING
- 10-BLOCK DIAGRAM
- 11-SPARE PATRS LIST
- 12-1COMPLETE PARTS LIST_FOR L42 HDTV10A
- 12-2COMPLETE PARTS LIST_FOR GV42L HDTV
- MAIN BOARD CIRCUIT DIAGRAM_FOR L42 HDTV10A
- MIAN BOARD CIRCUIT DIAGRAM_FOR GV42L HDTV
- MAIN BOARD PCB LAYOUT_FOR L42HDTV10A(LG/AUO)
- MAIN BOARD PCB LAYOUT_FOR GV42L HDTV_LG
- ASSEMBLY EXPLOSION DRAWING_FOR L42HDTV10A_AUO
- ASSEMBLY EXPLOSION DRAWING_FOR L42HDTV10A_LG
- ASSEMBLY EXPLOSION DRAWING_FOR GV42L HDTV_LG

CONFIDENTIAL – DO NOT COPY
Page 7-14
File No. SG-0198
4. Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the
rising edge of the clock. The DDR SDRAM has four independent banks, so two Bank Select
addresses (BA0 and BA1) are supported. The Bank Activate command must be applied before any
Read or Write operation can be executed. The delay from the Bank Activate command to the first
Read or Write command must meet or exceed the minimum RAS to CAS delay time (tRCD min).
Once a bank has been activated, it must be precharged before another Bank Activate command can
be applied to the same bank. The minimum time interval between interleaved Bank Activate
commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min).