Service manual

CIRCUIT DESCRIPTION
5-17
April 2001
Part No. 001-9800-203
To determine the overall divide number of the
prescaler and main divider, the number of input pulses
required to produce one main divider output pulse can
be determined. Although the programmed “N” number
is 83 in this example, the divide number is always two
higher (85) because of reset cycles and other effects.
Therefore, the prescaler divides by 65 for 55 x 65 or
3575 input pulses. It then divides by 64 for 85 x 64 or
5440 input pulses. The overall divide number K is
therefore 3575 + 5440 or 9015. The VCO frequency of
450.750 MHz divided by 9015 equals 50 kHz which is
the fR input to the phase detector.
If the VCO frequency is not evenly divisible by
50 kHz, there is also a fractional-N number
programmed that provides the required fractional
divide number. Refer to the 800/900 MHz description
in Section 5.10.6 for more information.
NOTE: The formulas for calculating the N and A
divide numbers are described in Section 6.3.5.
5.7.6 LOCK DETECT
When the synthesizer is locked on frequency, the
LOCK output of U804 (pin 18) is a logic high voltage.
Then when the synthesizer is unlocked, this voltage is
low. A locked condition exists when the phase differ-
ence at the TCXO input is less than one cycle.
5.7.7 CHARGE PUMP
The charge pump circuit in U804 charges and
discharges C833-C836 in the loop filter to produce the
VCO control voltage. Resistors connected to the RN
and RF pins set the charge current. The RF pin resis-
tance is set by a digitally controlled potentiometer in
U802. This resistance changes with the frequency
band in order to minimize fractional-N spurious
signals. The loop filter provides low-pass filtering
which controls synthesizer stability and lockup time
and suppresses the loop reference frequency (50 kHz).
5.7.8 SHIFT REGISTER (U800, U801) AND
DIGITAL POTENTIOMETER (U802)
PROGRAMMING
Shift register U800 functions as an I/O port
expander, and shift register U801 functions as a D/A
converter to provide a 256-step output voltage for
adjusting transmitter power. In addition, the Q7 output
of U801 provides the transmit/receive signal. U802
contains four digitally controlled potentiometers that
are also adjustable in 256 steps.
These devices are cascaded together on the serial
bus so that data is shifted out of one device into
another. Programming is performed using the SPI
serial port of the microcontroller described in Section
5.3.1. The input to the internal shift register of these
devices is the DATA pin (U800/U801) or SDI pin
(U802), and the output of the last shift register stage in
U800 and U801 is the QS
pin. Therefore, serial data
on the Data line from the audio/logic board (J201, pin
14) is first shifted into U801, then U800, and then
U802.
Data is clocked through the devices by the
CLOCK signal (J201, pin 13) when the STROBE
input (J201, pin 12) is high and latched when it goes
low. Synthesizer IC U804 is also programmed by the
SPI port. However, data does not pass through the
other devices, and it is controlled by different
STROBE signal (J201, pin 1).
5.8 RECEIVER CIRCUIT DESCRIPTION (UHF
MODELS)
NOTE: The receiver block diagram is shown in
Figure 5-4.
5.8.1 FRONT END FILTER
The receive signal is fed from the antenna switch
circuit on the PA board to the receiver front end on the
RF board. The signal is fed through a section of
microstrip that is part of a quarter-wave line for the
antenna switch. Also part of the antenna switch circuit
is C201, CR200, and R200. Refer to Section 5.9.4 for
more antenna switch information.
The receive signal is applied to a two-pole band-
pass filter formed by ceramic resonators L200 and
L201, several capacitors, and PIN diodes CR201 and
CR202. The function of this filter is to attenuate
frequencies outside the receive band such as the first
injection, image, and half IF frequencies. The pass-
band frequency of the filter is shifted in four steps
using PIN diodes. These diodes are controlled by
microcontroller through the Q2 and Q3 outputs of shift
UHF SYNTHESIZER DESCRIPTION