Service manual

CIRCUIT DESCRIPTION
5-7
April 2001
Part No. 001-9800-203
and the data appears on data bus lines D0-D7. Chip
select is performed by pulling the CE1 input (pin 20)
low. The CE2 input is always pulled high by R114.
The A13 and A14 address lines can be connected by
changing jumpers if a 16K or 32K part is required.
Data is read from U107 by pulling the OE input (pin
22) low. Likewise, data is written by pulling the WE
input (pin 27) low. See the U104 description which
follows for more information.
Flash EPROM (U108)
As described in Section 5.3.1, U108 can store up
to 128K bytes of data. The memory space is arranged
as 32K of common code space and twelve 8K blocks
of bank code space. The A15 line of the microcon-
troller determines if common or bank code space is
selected. When A15 is high, common space is
selected, and when it is low, bank space is selected.
The A15 line controls the four two-input multi-
plexers in U109. When A15 is low, the A input is
connected to Y which routes the PG0-PG3 outputs of
the microcontroller to U108. PG0-PG3 then select the
desired bank. Then when A15 is high, the B input is
routed to Y and the A13-A15 address lines of the
microcontroller are routed to U108.
Therefore, when a data read or write to U108
occurs, the lower 13 bits of the address are specified
by address lines A0-A12 and the rest of the address is
specified as just described. The data appears on data
bus lines D0-D7. Data is read from U108 by pulling
the OE
input (pin 24) low, and data is written by
pulling the WE
input (pin 31) low. Refer to the
following U104 description for more information.
Chip select is provided by pulling the CE
input (pin
22) low.
Read/Write Strobe Select (U104A-D)
NAND gates U104C and U104B select the read
and write signals applied to U107 and U108. When a
memory read occurs, the R/W
output of the microcon-
troller goes high. This signal is inverted by U104C and
applied to the OE
of U108. When a memory write
operation occurs, the R/W
output of the microcon-
troller goes low. U104B is then enabled by the high
output of U104C, and the high E signal is inverted by
U104B and applied to the WE
pin of U107 and to
U104D.
NAND gates U104A and U104D provide gating
of the write signal to U108. Data is written to this
device only during Flash programming. Therefore,
when Flash programming occurs, the Q3 output (pin
16) of shift register U111 goes high which enables
U104A. A double inversion of the write signal then
occurs and it is applied to the WE
input of U108.
Latch Programming (U106, U110-U112)
Decoder U106 provides chip select to octal
latches U110, U111, and U112. When data is written
to U106 address space, a low signal is applied to chip
select input G2A
(pin 4) and a high signal is applied to
chip select input G1 (pin 6). The three address bits
applied to the A, B, and C inputs of U106 select one of
the eight outputs. When an output is selected, it goes
low.
Data is latched by U110-U112 on a rising edge of
a clock signal from U106. Therefore, when the U106
output is disabled, data is latched. The outputs of the
latches are enabled when the OC
input (pin 1) is low,
and the outputs are a high impedance state when it is
high.
5.4 RECEIVE AUDIO/DATA PROCESSING
NOTE: A block diagram of the audio and data
processing circuitry is shown in Figure 5-3.
5.4.1 AMPLIFIER (U301B)
The demodulated receive audio/data signal from
limiter/detector U201 in the receiver is applied to
amplifier U301B. The gain of this amplifier is
controlled by analog switch U307B. The gain is higher
for narrow-band (12.5 kHz) channels to compensate
for the lower detected signal level that results from the
lower deviation used with those channels. The gain is
approximately four with narrowband channels and two
with wideband (25 kHz) channels.
The control input of U307B (pin 5) is low for
narrowband channels and high for wideband chan-
nels. When it is high, the switch is closed and R327 is
switched into the circuit. This adds more feedback
which decreases the gain. The control signal comes
from the Q0 output (pin 19) of latch U111. Transistor
Q305 inverts this signal and also provides level
AUDIO/LOGIC DESCRIPTION (ALL MODELS)