Service manual

CIRCUIT DESCRIPTION
5-6
April 2001
Part No. 001-9800-203
PE7 - This input senses the voltage on the IN3 pin of
Option 1 slot wire-out W301.
Serial Peripheral Interface Port (SPI), OR Gate (U103)
This serial port is formed by the MOSI, MISO,
and SCK pins (31, 30, 32) of the microcontroller. It is
a synchronous port which means that a clock signal is
used to indicate when data on the data line is valid.
This port has both master and slave configurations and
in this application, the master configuration is always
used. In the master configuration the microcontroller
generates the clock and other signals.
MOSI (Master Out, Slave In) - This is the serial data
output for the port.
MISO (Master In, Slave Out) - This is the serial data
input for this port.
SCK - Serial clock output. This pin provides the clock
signal to all devices served by this port.
This port provides two-way serial data communi-
cation with EEPROM U102 (high tier and data
models) and microcontroller U2 on the display board
(high tier only). In addition, it provides programming
data to the RF board for shift registers U800 and
U801, digital potentiometer U802, and synthesizer IC
U804 (see Section 5.7.8). It also provides program-
ming data to shift register U305 (on the audio/logic
board) which controls the squelch level.
OR gates U103A-D provide routing of the serial
port signals to the RF and display boards. When the
PD5 output (pin 33) of the microcontroller goes low,
U103A and U103B route the data and clock signals to
the RF board and shift register U305. Then when the
Q4 output (pin 15) of latch U110 goes low, U103D
routes the clock signal to the display board and U103C
routes the display board data signal to the MISO pin.
When communicating with the display board, PD5
goes high to block the data path through U103A and
U103B.
Asynchronous Serial Communications Interface (SCI)
This is a full duplex serial port formed by the
RxD (data input) and TxD (data output) pins (28, 29)
of the microcontroller. This port uses a standard non-
return-to-zero (NRZ) format consisting of one start bit,
eight or nine data bits, and one stop bit.
This port is used to provide data communication
with the computer used to program the transceiver.
Connection is made via the front panel microphone
connector. Another use for this port is data communi-
cation with an external data device such as a modem.
Connection is made via connector J301. Communica-
tion cannot occur simultaneously over both of these
paths.
Other General Purpose Inputs and Outputs
The PA0-PA7 pins are used for general purpose
inputs and outputs as follows:
PA0 - Input for PTT signal from the microphone jack
and W302/W312 option slot wire-outs. This signal is
low when the transmitter is keyed.
PA1 - Input for the receive LTR or Call Guard data
signal.
PA2 - Service request input from microcontroller U2
on the display board. This tells U101 that it has data to
send on the SPI bus described previously.
PA3 - Input from the Option 1 pin of modem
connector J301.
PA4/PA5 - Transmit LTR/Call Guard data output.
These two outputs are used to create a pseudo sine-
wave signal. See Section 5.5.4 for more information.
PA6 - Output for supervisory tones generated by the
microcontroller such as busy and out-of-range.
PA7 - Input from the squelch circuit (see Section
5.4.4). When the received signal strength increases to
the squelch threshold level, this input goes high. The
microcontroller uses this information to determine
when receive data is valid and to control audio
muting.
5.3.2 MEMORY AND LATCH PROGRAMMING
RAM U107 (High Tier and Data Models)
When a data read or write to U107 occurs, the
location in U107 is selected by address lines A0-A12,
AUDIO/LOGIC DESCRIPTION (ALL MODELS)