User guide

EQ100 Motherboard User Guide V2.0
43
North Bridge Configuration
Figure 33: North Bridge Configuration Screen.
Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according to the
DRAM Serial Presence Detect (SPD). When disabled, you can manually set the
DRAM timing parameters through the DRAM sub-items.
Configuration options: [Disabled] [Enabled]
The following sub-items appear when this item is disabled.
DRAM CAS# Latency [5 DRAM Clocks]
Controls the latency between the SDRAM read command and the time the
data actually becomes available. Configuration options: [5 DRAM Clocks] [4
DRAM Clocks] [3 DRAM Clocks]
DRAM RAS# to CAS# Delay [6 DRAM Clocks]
Controls the latency between the DDR SDRAM active command and the
read/write command. Configuration options: [2 DRAM Clocks] [3 DRAM
Clocks] [4 DRAM Clocks] [5 DRAM Clocks] [6 DRAM Clocks]
DRAM RAS# Precharge [6 DRAM Clocks]
Controls the idle clocks after issuing a precharge command to the DDR
SDRAM Configuration options: [2 DRAM Clocks] [3 DRAM Clocks] [4 DRAM
Clocks] [5 DRAM Clocks] [6 DRAM Clocks]
DRAM RAS# Activate to Precharge [15 DRAM Clocks]
Configuration options: [4 DRAM Clocks] ~ [15 DRAM Clocks]
Memory Hole [Disabled]
Sets or disables the software memory remapping around the memory hole.
Configuration options: [Disabled] [15MB - 16MB]