Service manual

PVOUT[15:0]
RP50
47
1 8
2
3
4 5
6
7
PCLK1
PHS1 P{8}
PVS1
TS0ERRP{2}
TS0DATA4
TS0DATA3
TS0DATA0
U29C
PWM2030
VOUT0
C19
VOUT1
B19
VOUT2
A19
VOUT3
D18
VOUT4
C18
VOUT5
B18
VOUT6
A18
VOUT7
D17
VOUT8
C17
VOUT9
B17
VOUT10
A17
VOUT11
C16
VOUT12
B16
VOUT13
D15
VOUT14
C15
VOUT15
B15
VSYNCO0
D14
HSYNCO0
A15
PIXCLKO0
C14
TS0DATA0
AE23
TS0DATA1
AD23
TS0DATA2
AF24
TS0DATA3
AE24
TS0DATA4
AD25
TS0DATA5
AD26
TS0DATA6
AC24
TS0DATA7
AC25
TS0REQ
AB24
TS0SYNC
AB23
TS0VALID
AC26
TS0CLK
AB25
PIXCLKO1
A13
HSYNCO1
B14
VSYNCO1
A14
TS1REQ
W26
TS1CLK
V23
TS1VALID
W24
TS1SYNC
W25
TS1DATA0
AB26
TS1DATA1
AA23
TS1DATA2
AA24
TS1DATA3
AA25
TS1DATA4
AA26
TS1DATA5
Y24
TS1DATA6
Y25
TS1DATA7
W23
TSOCLK
N23
TSOVALID
N25
TSOSYNC
N24
TSODATA0
R24
TSODATA1
R25
TSODATA2
R26
TSODATA3
P23
TSODATA4
P24
TSODATA5
P25
TSODATA6
P26
TSODATA7
N26
TS2REQ
U23
TS2CLK
U24
TS2VALID
V25
TS2SYNC
V26
TS2DATA
V24
TS3REQ
T25
TS3CLK
R23
TS3VALID
U26
TS3SYNC
T24
TS3DATA
U25
TSCLKI
M23
TS0VALIDP{2}
TS0SYNCP{2}
TS0DATA[7:0]P{2}
TS0CLKP{2}
TS0DATA2
TS0DATA1
TS0DATA6
TS0DATA7
TS0DATA5
Digital Video Signal output
RVOUT12
RHS2
RCLK2
RVOUT15
RVOUT14
RVOUT13
RVOUT0
RVOUT7
RVOUT6
RVOUT5
RVOUT4
RVS2
RHS1
RCLK1
RVOUT3
RVOUT2
RVOUT1
RVOUT11
RVOUT10
RVOUT9
RVOUT8
RVS1
PVOUT2
PVOUT9
PVOUT5
PVOUT3
PVOUT7
PVOUT4
PVOUT10
PVOUT0
PVOUT12
PVOUT14
PVOUT15
PVOUT13
PVOUT8
PVOUT1
PVOUT6
PVOUT11
RP53
47
18
2
3
45
6
7
RP51
47
18
2
3
45
6
7
RP52
47
1 8
2
3
4 5
6
7
RP55
47_NC
1 8
2
3
4 5
6
7
RP54
47
1 8
2
3
4 5
6
7
zSystem Control
The PWM2030 incorporates a TX49 core core ( 64-bit MCU core ) and a CRISC (Control 32-bit RISC
processor
) for system control. The TX49 core issues instructions to the CRISC as well as to the
peripheral controllers such as PCIC (
PCI Controller) , USB, and UART. Based on the instructions sent
from the TX49 core, the CRISC controls decoders such as video (VDEC), and audio (AUDIO),
System Control Detail Block Diagram
zUnited Memory
DDR SDRAM ( U35 , U36 ) is externally connected to the PWM2030. In addition to the CRISC and
TX49 core, the unified memory allows all internal decoders can share data via VMMS (
Virtual Multi-port
Memory System ,Controls external DDR-SDRAM 64 bits) , which reduces external memory types and
capacities.
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