Specifications

D:\D\inter61a\INTERRUP.A Saturday, January 08, 2011 11:31 AM

Desc: generated by the CPU on various occurrences which may be of interest

to a debugger program

Note: events which may trigger the interrupt:

Instruction address breakpoint fault - will return to execute inst

Data address breakpoint trap - will return to following instruction

General detect fault, debug registers in use

Task-switch breakpoint trap

undocumented 386/486 opcode F1h - will return to following instruc

SeeAlso: INT 03"CPU"

--------H-02---------------------------------

INT 02 C - external hardware - NON-MASKABLE INTERRUPT

Desc: generated by the CPU when the input to the NMI pin is asserted

Notes: return address points to start of interrupted instruction on 80286+

on the 80286+, further NMIs are disabled until the next IRET

instruction, but one additional NMI is remembered by the hardware

and will be serviced after the IRET instruction reenables NMIs

maskable interrupts may interrupt the NMI handler if interrupts are

enabled

although the Intel documentation states that this interrupt is

typically used for power-failure procedures, it has many other uses

on IBM-compatible machines:

Memory parity error: all except Jr, CONV, and some machines

without memory parity

Breakout switch on hardware debuggers

Coprocessor interrupt: all except Jr and CONV

Keyboard interrupt: Jr, CONV

I/O channel check: CONV, PS50+

Disk-controller power-on request: CONV

System suspend: CONV

Real-time clock: CONV

System watch-dog timer, time-out interrupt: PS50+

DMA timer time-out interrupt: PS50+

Low battery: HP 95LX

Module pulled: HP 95LX

--------m-02----SI0714-----------------------

INT 02 U - STB RAPIDMAP.SYS - ???

SI = 0714h

ES:DI -> ???

Return: ???

SeeAlso: INT 67/AX=6100h"STB",PORT 00E1h"STB"

--------C-03---------------------------------

-5-

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